LTC1274/LTC1277 WBLOCK DIAGRA SLTC1274 CSAMPLE A V IN DD ZEROING SWITCHES V V REF SS (0V FOR UNIPOLAR MODE OR 2.42V REF –5V FOR BIPOLAR MODE) REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 SUCCESSIVE APPROXIMATION • D11 OUTPUT LATCHES • REGISTER • D0 INTERNAL CONTROL LOGIC CLOCK LTC1274 • BD SLEEP CONVST RD CS BUSY LTC1277 CSAMPLE A + IN VDD A – IN ZEROING SWITCHES V V REF SS (0V FOR UNIPOLAR MODE OR 2.42V REF –5V FOR BIPOLAR MODE) REFRDY COMPARATOR 12-BIT CAPACITIVE DAC AGND DGND 12 D7 SUCCESSIVE APPROXIMATION • • REGISTER OUTPUT LATCHES • • • D1/9 D0/8 INTERNAL CONTROL LOGIC CLOCK LTC1277 • BD HBEN SLEEP NAP CONVST RD CS BUSY VLOGIC 3V OR 5V TEST CIRCUITSLoad Circuits for Access TimingLoad Circuits for Output Float Delay 5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t9) B) HIGH-Z TO VOL (t9) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1274/77 • TC02 1274/77 • TC01 9