Datasheet LTC1274, LTC1277 (Analog Devices) - 8

LTC1274/LTC1277
U U U PI FU CTIO S RD (Pin 20):
Read Input. This enables the output drivers
D7 to D4* (Pins 8 to 11):
Three-State Data Outputs. when CS is low.
DGND (Pin 12):
Digital Ground.
CS (Pin 21):
The Chip Select input must be low for the ADC
D3/11 to D0/8* (Pins 13 to 16):
Three-State Data Outputs. to recognize CONVST and RD inputs. D11 is the Most Significant Bit.
BUSY (Pin 21):
The BUSY output shows the converter
V
status. It is low when a conversion is in progress. The
LOGIC (Pin 17):
5V or 3V Digital Power Supply. This pin allows a 5V or 3V logic interface with the processor. All rising Busy edge can be used to latch the conversion logic outputs (Data Bits, BUSY and REFRDY) will swing result. between 0V and VLOGIC.
VSS (Pin 23):
Negative 5V Supply. Negative 5V will select
HBEN (Pin 18):
High Byte Enable Input. The four Most bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie Significant Bits will appear at Pins 13 to 16 when this pin this pin to analog ground to select unipolar operation. is high. The LTC1277 uses straight binary for unipolar
VDD (Pin 24):
Positive 5V Supply. Bypass to AGND (10µF mode and offset binary for bipolar mode. tantalum in parallel with 0.1µF ceramic).
CONVST (Pin 19):
Conversion Start Signal. This active low
LTC1277
signal starts a conversion on its falling edge (to recognize CONVST, CS has to be low).
A +
+ –
IN (Pin 1):
Positive Analog Input. (AIN – AIN ) = 0V to
RD (Pin 20):
Read Input. This enables the output drivers 4.096V, unipolar (VSS = 0V) or ±2.048V, bipolar (VSS = –5V). when CS is low.
A – IN (Pin 2):
Negative Analog Input. This pin needs to be
CS (Pin 21):
The Chip Select input must be low for the ADC free of noise during conversion. For single-ended inputs to recognize CONVST and RD inputs. tie A – IN to analog ground.
BUSY (Pin 22):
The BUSY output shows the converter
VREF (Pin 3):
2.42V Reference Output. Bypass to AGND status. It is low when a conversion is in progress. (10µF tantalum in parallel with 0.1µF ceramic). VREF can be overdriven positive with an external reference voltage.
VSS (Pin 23):
Negative 5V Supply. Negative 5V will select bipolar operation. Bypass to AGND with 0.1µF ceramic. Tie
AGND (Pin 4):
Analog Ground. this pin to analog ground to select unipolar operation.
REFRDY (Pin 5):
Reference Ready Signal. It goes high
V
when the reference has settled after SLEEP indicating that
DD (Pin 24):
5V Positive Supply. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). the ADC is ready to sample.
SLEEP (Pin 6):
SLEEP Mode Input. Tie this pin to low to put
Table 1. LTC1277 Two-Byte Read Data Bus Status
the ADC in Sleep mode and save power (REFRDY will go
DATA OUTPUTS D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8
LOW). The device will draw 1µA in this mode. Low Byte DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
NAP (Pin 7):
NAP Mode Input. Pulling this pin low will shut High Byte Low Low Low Low DB11 DB10 DB9 DB8 down all currents in the ADC except the reference. In this mode the ADC draws 180µA. Wake-up from Nap mode is about 620ns. *The LTC1277 bipolar mode is in offset binary. 8