Datasheet AD8091, AD8092 (Analog Devices) - 7

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AD8091/AD8092 MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092 If the rms signal levels are indeterminate, then consider the package is limited by the associated rise in junction temperature worst case when VOUT = VS/4 for RL to midsupply (TJ) on the die. The plastic encapsulating the die locally reaches 2 ⎛ V ⎞ the junction temperature. At approximately 150°C, which is the S ⎜ ⎟ ⎝ 4 ⎠ glass transition temperature, the plastic changes its properties. = × + D P (V I S S ) Even temporarily exceeding this temperature limit may change RL the stresses that the package exerts on the die, permanently In single-supply operation with RL referenced to −VS, the worst shifting the parametric performance of the AD8091/AD8092. case is VOUT = VS/2. Exceeding a junction temperature of 175°C for an extended Airflow increases heat dissipation, effectively reducing θJA. Also, period of time can result in changes in the silicon devices, more metal directly in contact with the package leads from potentially causing failure. metal traces, through holes, ground, and power planes reduces The still-air thermal properties of the package (θJA), the ambient the θJA. Care must be taken to minimize parasitic capacitances temperature (TA), and the total power dissipated in the package at the input leads of high speed op amps as discussed in the (PD) can be used to determine the junction temperature of the die. Input Capacitance section. The junction temperature can be calculated as Figure 4 shows the maximum safe power dissipation in the = + package vs. the ambient temperature for the SOIC-8 J T × A T ( DP θJA) (125°C/W), SOT23-5 (180°C/W), and MSOP-8 (150°C/W) on a The power dissipated in the package (PD) is the sum of the JEDEC standard four-layer board. quiescent power dissipation and the power dissipated in the
2.0
package due to the load drive for all outputs. The quiescent
TJ = 150°C
power is the voltage between the supply pins (V
)
S) times the
(W
quiescent current (IS). Assuming that the load (RL) is referenced
N 1.5 IO SOIC-8
to midsupply, then the total drive power is V
T
S/2 × IOUT, some of
A P
which is dissipated in the package and some in the load
ISSI MSOP-8
(V
D
OUT × IOUT). The difference between the total drive power and
R 1.0 E
the load power is the drive power dissipated in the package.
W PO
P = + −
M
D quiescent power (total drive power load power)
U SOT23-5 M 0.5 XI
2
A M
P = V V V V I 4 D ( × S S ) ⎛⎛ ⎞ ⎛ ⎞⎞ + ⎜ S × OUT − ⎜ OUT ⎟⎟ ⎜⎜⎜ ⎟⎟ ⎜ ⎟⎟ 00 ⎝⎝ 2 R R 9- L ⎠ ⎝ L ⎠⎠ 85
0
02
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
RMS output voltages should be considered. If RL is referenced to
AMBIENT TEMPERATURE (°C)
−V S, as in single-supply operation, then the total drive power is Figure 4. Maximum Power Dissipation vs. VS × IOUT. Temperature for a Four-Layer Board Rev. C | Page 7 of 20 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAMS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION MAXIMUM POWER DISSIPATION TYPICAL PERFORMANCE CHARACTERISTICS LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS POWER SUPPLY BYPASSING GROUNDING INPUT CAPACITANCE INPUT-TO-OUTPUT COUPLING DRIVING CAPACITIVE LOADS OVERDRIVE RECOVERY ACTIVE FILTERS SYNC STRIPPER SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER OUTLINE DIMENSIONS ORDERING GUIDE