Datasheet MCP6241, MCP6241R, MCP6241U, MCP62412, MCP62414 (Microchip) - 9

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MCP6241/1R/1U/2/4 3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6241 MCP6241R MCP6241U Symbol Description
MSOP, PDIP, SOT-23-5, DFN SOT-23-5 SOT-23-5 SOIC SC-70 6 6 1 1 4 VOUT Analog Output 2 2 4 4 3 VIN– Inverting Input 3 3 3 3 1 VIN+ Non-inverting Input 7 7 5 2 5 VDD Positive Power Supply 4 4 2 5 2 VSS Negative Power Supply 1, 5, 8 1, 5, 8 — — — NC No Internal Connection 9 — — — — EP Exposed Thermal Pad (EP); must be connected to VSS.
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6242 MCP6244 Symbol Description
MSOP, PDIP, SOIC PDIP, SOIC, TSSOP 1 1 VOUTA Analog Output (op amp A) 2 2 VINA– Inverting Input (op amp A) 3 3 VINA+ Non-inverting Input (op amp A) 8 4 VDD Positive Power Supply 5 5 VINB+ Non-inverting Input (op amp B) 6 6 VINB– Inverting Input (op amp B) 7 7 VOUTB Analog Output (op amp B) — 8 VOUTC Analog Output (op amp C) — 9 VINC– Inverting Input (op amp C) — 10 VINC+ Non-inverting Input (op amp C) 4 11 VSS Negative Power Supply — 12 VIND+ Non-inverting Input (op amp D) — 13 VIND– Inverting Input (op amp D) — 14 VOUTD Analog Output (op amp D)
3.1 Analog Outputs
Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to The output pins are low-impedance voltage sources. ground and VDD is connected to the supply. VDD will need bypass capacitors.
3.2 Analog Inputs 3.4 Exposed Thermal Pad (EP)
The non-inverting and inverting inputs are high- impedance CMOS inputs with low bias currents. There is an internal electrical connection between the Exposed Thermal Pad (EP) and the V
3.3 Power Supply (V
SS pin; they must
SS and VDD)
be connected to the same potential on the Printed Circuit Board (PCB). The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. © 2008 Microchip Technology Inc. DS21882D-page 9 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85˚C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125˚C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information