Datasheet MCP6241, MCP6241R, MCP6241U, MCP62412, MCP62414 (Microchip) - 3

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MCP6241/1R/1U/2/4 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Analog Input Pins (VIN+, VIN–)...±2 mA
††
See
Section 4.1.2 “Input Voltage and Current Limits”
. Analog Inputs (VIN+, VIN–) †† .. VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V Difference Input Voltage .. |VDD – VSS| Output Short Circuit Current .. Continuous Current at Output and Supply Pins ..±30 mA Storage Temperature .. –65° C to +150°C Maximum Junction Temperature (TJ)... .+150°C ESD Protection On All Pins (HBM; MM) .. ≥ 4 kV; 300V
DC ELECTRICAL CHARACTERISTICS Electrical Characteristics
: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, V ≈ CM = VDD/2, RL = 100 kΩ to VDD/2 and VOUT VDD/2.
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -5.0 — +5.0 mV VCM = VSS Extended Temperature VOS -7.0 — +7.0 mV TA= -40°C to +125°C, VCM = VSS
(Note 1)
Input Offset Drift with ΔVOS/ΔTA — ±3.0 — µV/°C TA= -40°C to +125°C, Temperature VCM = VSS Power Supply Rejection PSRR — 83 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current: IB — ±1.0 — pA At Temperature IB — 20 — pA TA = +85°C At Temperature IB — 1100 — pA TA = +125°C Input Offset Current IOS — ±1.0 — pA Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||3 — Ω||pF
Common Mode
Common Mode Input Range VCMR VSS – 0.3 — VDD + 0.3 V Common Mode Rejection Ratio CMRR 60 75 — dB VCM = -0.3V to 5.3V, VDD = 5V Open-Loop Gain DC Open-Loop Gain AOL 90 110 — dB VOUT = 0.3V to VDD – 0.3V, (large signal) VCM = VSS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 35 — VDD – 35 mV RL = 10 kΩ, 0.5V Input Overdrive Output Short-Circuit Current ISC — ±6 — mA VDD = 1.8V ISC — ±23 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 5.5 V Quiescent Current per Amplifier IQ 30 50 70 µA IO = 0, VCM = VDD – 0.5V
Note 1:
The SC-70 package is only tested at +25°C. © 2008 Microchip Technology Inc. DS21882D-page 3 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85˚C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125˚C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6241/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information