Datasheet LTC6943 (Analog Devices) - 6

LTC6943
U U W U APPLICATIO S I FOR ATIO
precision DVM, the change of the voltage across CH with
Shielding the Sampling Capacitor for Very High CMRR
respect to an input CM voltage variation. During the Internal or external parasitic capacitors from the C+ pin(s) sampling and holding mode, charges are being trans- to ground affect the CMRR of the LTC6943 (Figure 1). ferred and minute voltage transients will appear across the The common mode error due to the internal junction holding capacitor. Although the RON on the switches is low capacitances of the C+ Pin(s) 1 and 9 is cancelled through enough to allow fast settling, as the sampling frequency internal circuitry. The C+ pin, therefore, should be used as increases, the rate of charge transfer increases and the the top plate of the sampling capacitor. A shield placed average voltage measured with a DVM across it will underneath the sampling capacitor and connected to C– increase proportionally; this causes the CMRR of the helps to boost the CMRR to 120dB (Figure 5). sampled data system, as seen by a “continuous” instru- ment (DVM), to decrease (Figure 2). Excessive external parasitic capacitance between the C– pins and ground indirectly degrades CMRR; this becomes
Switch Charge Injection
visible especially when the LTC6943 is used with clock frequencies above 2kHz. Because of this, if a shield is Figure 3 shows one out of the eight switches of the used, the parasitic capacitance between the shield and LTC6943, configured as a basic sample-and-hold circuit. circuit ground should be minimized. When the switch opens, a ‘‘hold step’’ is observed and its magnitude depends on the value of the input voltage. It is recommended that the outer plate of the sampling Figure 4 shows charge injected into the hold capacitor. For capacitor be connected to the C– pin(s). instance, a 2pCb of charge injected into a 0.01µF capacitor causes a 200µV hold step. As shown in Figure 4, there is
COSC Pin (14)
a predictable and repeatable charge injection cancellation The COSC pin can be used with an external capacitor, COSC, when the input voltage is close to half the supply voltage connected from Pin 14 to Pin 15, to modify the internal of the LTC6943. This is a unique feature of this product, oscillator frequency. If Pin 16 is floating, the internal 24pF containing charge-balanced switches fabricated with a capacitor, plus any external interpin capacitance, set the self-aligning gate CMOS process. Any switch of the oscillator frequency around 190kHz with ±5V supply. The LTC6943, when powered with symmetrical dual supplies, typical performance characteristics curves provide the will sample-and-hold small signals around ground with- necessary information to set the oscillator frequency for out any significant error. various power supply ranges. Pin 14 can also be driven with an external CMOS level clock to override the internal 140 oscillator. CS = CH = 1µF 120 CS = 1µF, CH = 0.1µF 5V 100 1 5 + 80 1/2 LTC1013 V 1/8 LTC6943 OUT CMRR (dB) – 60 VIN 1000pF –5V 40 V+ SAMPLE 20 HOLD TO PIN 14 100 1k 10k 100k 0V 6943 • AI03 fOSC (Hz) 6943 • AI02
Figure 2. CMRR vs Sampling Frequency Figure 3
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