Datasheet AD842 (Analog Devices) - 9

link to page 9 link to page 9 link to page 10 link to page 9 link to page 9 link to page 10
Data Sheet AD842 THEORY OF OPERATION OFFSET NULLING 10V 10mV 20ns
The input offset voltage of the AD842 is very low for a high
100% 90% OUTPUT:
speed op amp, but if additional nulling is required, the circuit
10V/DIV
shown in Figure 28 can be used.
SETTLING TIME OUTPUT
Figure 29 and Figure 31 show the settling performance of the
ERROR: 0.02%/DIV
AD842 in the test circuit shown in Figure 30. Settling time is the interval of time from the application of an ideal step function input until the closed-loop amplifier output
10%
enters and remains within a specified error band.
0%
029 This definition encompasses the major components that 09477- Figure 29. 0.01% Settling Time comprise settling time. They include the fol owing: Figure 30 shows how measurement of the AD842 0.01% settling • Propagation delay through the amplifier. in 100 ns is accomplished by amplifying the error signal from a • Slewing time to approach the final output value. false summing junction with a very high speed proprietary • Time of recovery from the overload associated with hybrid error amplifier specially designed to enable testing of slewing. small settling errors. Under test, the device drives a 300 Ω load. • Linear settling to within the specified error band. The input to the error amp is clamped to avoid possible Expressed in these terms, the measurement of settling time problems associated with the overdrive recovery of the must be accurate to assure the user that the amplifier is worth oscil oscope input amplifier. The error amp gains the error from consideration for the application. the false summing junction by 15, and it contains a gain vernier to fine trim the gain.
+VS 10kΩ 0.1µF
Figure 31 shows the long-term stability of the settling
3 13 2.2µF
characteristics of the AD842 output after a 10 V step. There is
4
no evidence of settling tails after the initial transient recovery
11 VOUT V 10 IN AD842
time. The use of a junction isolated process, together with
5 6 RL
careful layout, avoids these problems by minimizing the effects
0.1µF
of transistor isolation capacitance discharge and thermal y
2.2µF
028 induced shifts in circuit operating points. These problems do
–VS
not occur even under high output current conditions. 09477- Figure 28. Offset Nulling (PDIP)
ERROR TEK AMP (×15) 7A13 TEK 7603 OSCILLOSCOPE TEK 7A16 HP6263 DDD5109 499Ω 1kΩ FLAT-TOP PULSE GENERATOR 499Ω 1kΩ 0.1µF 50Ω +15V 2.2µF 11 4 FET PROBE TEK P6201 AD842 10 5 0.1µF 499Ω 499Ω 6 2.2µF
030
–15V
09477- Figure 30. Settling Time Test Circuit (PDIP) Rev. F | Page 9 of 16 Document Outline Features Applications Connection Diagrams General Description Product Highlights Table of Contents Revision History Specifications Electrical Characteristics—±15 V Operation Absolute Maximum Ratings Thermal Characteristics ESD Caution Metalization Photograph Typical Performance Characteristics Theory of Operation Offset Nulling Settling Time Grounding and Bypassing Capacitive Load Driving Ability Using a Heat Sink Terminated Line Driver Overdrive Recovery Outline Dimensions Ordering Guide