Datasheet ATmega64A - Complete - 2

– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface • Atmel QTouch® library support – Capacitive touch buttons, sliders and wheels – Atmel QTouch and QMatrix acquisition – Up to 64 sense channels • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture Mode – Real Time Counter with Separate Oscillator – Two 8-bit PWM Channels – 6 PWM Channels with Programmable Resolution from 1 to 16 Bits – Output Compare Modulator – 8-channel, 10-bit ADC • 8 Single-ended Channels • 7 Differential Channels • 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USARTs – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby – Software Selectable Clock Frequency – ATmega103 Compatibility Mode Selected by a Fuse – Global Pull-up Disable • I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V • Speed Grades – 0 - 16MHz Atmel ATmega64A [DATASHEET] 2 Atmel-8160E-ATmega64A_Datasheet_Complete-09/2015 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. ATmega103 and ATmega64A Compatibility 5.1. ATmega103 Compatibility Mode 6. Pin Configurations 6.1. Pin Descriptions 6.1.1. VCC 6.1.2. GND 6.1.3. Port A (PA7:PA0) 6.1.4. Port B (PB7:PB0) 6.1.5. Port C (PC7:PC0) 6.1.6. Port D (PD7:PD0) 6.1.7. Port E (PE7:PE0) 6.1.8. Port F (PF7:PF0) 6.1.9. Port G (PG4:PG0) 6.1.10. RESET 6.1.11. XTAL1 6.1.12. XTAL2 6.1.13. AVCC 6.1.14. AREF 6.1.15. PEN 7. Resources 8. Data Retention 9. About Code Examples 10. Capacitive Touch Sensing 11. AVR CPU Core 11.1. Overview 11.2. ALU – Arithmetic Logic Unit 11.3. Status Register 11.3.1. SREG – The AVR Status Register 11.4. General Purpose Register File 11.4.1. The X-register, Y-register and Z-register 11.5. Stack Pointer 11.6. Instruction Execution Timing 11.7. Reset and Interrupt Handling 11.7.1. Interrupt Response Time 12. AVR Memories 12.1. Overview 12.2. In-System Reprogrammable Flash Program Memory 12.3. SRAM Data Memory 12.3.1. Data Memory Access Times 12.4. EEPROM Data Memory 12.4.1. EEPROM Read/Write Access 12.4.2. EEPROM Write during Power-down Sleep Mode 12.4.3. Preventing EEPROM Corruption 12.5. I/O Memory 12.6. External Memory Interface 12.6.1. Features 12.6.2. Overview 12.6.3. ATmega103 Compatibility 12.6.4. Using the External Memory Interface 12.6.5. Address Latch Requirements 12.6.6. Pull-up and Bus-keeper 12.6.7. Timing 12.6.8. Using all Locations of External Memory Smaller than 64 Kbytes 12.6.9. Using all 64 Kbytes Locations of External Memory 12.7. Register Description 12.7.1. EEARL – The EEPROM Address Register Low 12.7.2. EEARH – The EEPROM Address Register High 12.7.3. EEDR – The EEPROM Data Register 12.7.4. EECR – The EEPROM Control Register 12.7.5. MCUCR – MCU Control Register 12.7.6. XMCRA – External Memory Control Register A 12.7.7. XMCRB – External Memory Control Register B 13. System Clock and Clock Options 13.1. Clock Systems and their Distribution 13.1.1. CPU Clock – clkCPU 13.1.2. I/O Clock – clkI/O 13.1.3. Flash Clock – clkFLASH 13.1.4. Asynchronous Timer Clock – clkASY 13.1.5. ADC Clock – clkADC 13.2. Clock Sources 13.3. Default Clock Source 13.4. Crystal Oscillator 13.5. Low-frequency Crystal Oscillator 13.6. External RC Oscillator 13.7. Calibrated Internal RC Oscillator 13.8. External Clock 13.9. Timer/Counter Oscillator 13.10. Register Description 13.10.1. XDIV – XTAL Divide Control Register 13.10.2. OSCCAL – The Oscillator Calibration Register 14. Power Management and Sleep Modes 14.1. Sleep Modes 14.2. Idle Mode 14.3. ADC Noise Reduction Mode 14.4. Power-down Mode 14.5. Power-save Mode 14.6. Standby Mode 14.7. Extended Standby Mode 14.8. Minimizing Power Consumption 14.8.1. Analog-to-Digital Converter (ADC) 14.8.2. Analog Comparator 14.8.3. Brown-out Detector 14.8.4. Internal Voltage Reference 14.8.5. Watchdog Timer 14.8.6. Port Pins 14.8.7. JTAG Interface and On-chip Debug System 14.9. Register Description 14.9.1. MCUCR – MCU Control Register 15. System Control and Reset 15.1. Resetting the AVR 15.2. Reset Sources 15.2.1. Power-on Reset 15.2.2. External Reset 15.2.3. Brown-out Detection 15.2.4. Watchdog Reset 15.3. Internal Voltage Reference 15.3.1. Voltage Reference Enable Signals and Start-up Time 15.4. Watchdog Timer 15.5. Timed Sequences for Changing the Configuration of the Watchdog Timer 15.5.1. Safety Level 0 15.5.2. Safety Level 1 15.5.3. Safety Level 2 15.6. Register Description 15.6.1. MCUCSR – MCU Control and Status Register 15.6.2. WDTCR – Watchdog Timer Control Register 16. Interrupts 16.1. Interrupt Vectors in ATmega64A 16.1.1. Moving Interrupts Between Application and Boot Space 16.2. Register Description 16.2.1. MCUCR – MCU Control Register 17. External Interrupts 17.1. Register Description 17.1.1. EICRA – External Interrupt Control Register A 17.1.2. EICRB – External Interrupt Control Register B 17.1.3. EIMSK – External Interrupt Mask Register 17.1.4. EIFR – External Interrupt Flag Register 18. I/O Ports 18.1. Overview 18.2. Ports as General Digital I/O 18.2.1. Configuring the Pin 18.2.2. Reading the Pin Value 18.2.3. Digital Input Enable and Sleep Modes 18.2.4. Unconnected Pins 18.3. Alternate Port Functions 18.3.1. Alternate Functions of Port A 18.3.2. Alternate Functions of Port B 18.3.3. Alternate Functions of Port C 18.3.4. Alternate Functions of Port D 18.3.5. Alternate Functions of Port E 18.3.6. Alternate Functions of Port F 18.3.7. Alternate Functions of Port G 18.4. Register Description 18.4.1. SFIOR – Special Function IO Register 18.4.2. PORTA – Port A Data Register 18.4.3. DDRA – Port A Data Direction Register 18.4.4. PINA – Port A Input Pins Address 18.4.5. PORTB – The Port B Data Register 18.4.6. DDRB – The Port B Data Direction Register 18.4.7. PINB – The Port B Input Pins Address 18.4.8. PORTC – The Port C Data Register 18.4.9. DDRC – The Port C Data Direction Register 18.4.10. PINC – The Port C Input Pins Address 18.4.11. PORTD – The Port D Data Register 18.4.12. DDRD – The Port D Data Direction Register 18.4.13. PIND – The Port D Input Pins Address 18.4.14. PORTE – The Port E Data Register 18.4.15. DDRE – The Port E Data Direction Register 18.4.16. PINE – The Port E Input Pins Address 18.4.17. PORTF – The Port F Data Register 18.4.18. DDRF – The Port F Data Direction Register 18.4.19. PINF – The Port F Input Pins Address 18.4.20. PORTG – The Port G Data Register 18.4.21. DDRG – The Port G Data Direction Register 18.4.22. PING – The Port G Input Pins Address 19. Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers 19.1. Overview 19.2. Internal Clock Source 19.3. Prescaler Reset 19.4. External Clock Source 19.5. Register Description 19.5.1. SFIOR – Special Function IO Register 20. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 20.1. Features 20.1.1. Restrictions in ATmega103 Compatibility Mode 20.2. Overview 20.2.1. Registers 20.2.2. Definitions 20.2.3. Compatibility 20.3. Accessing 16-bit Registers 20.3.1. Reusing the Temporary High Byte Register 20.4. Timer/Counter Clock Sources 20.5. Counter Unit 20.6. Input Capture Unit 20.6.1. Input Capture Pin Source 20.6.2. Noise Canceler 20.6.3. Using the Input Capture Unit 20.7. Output Compare Units 20.7.1. Force Output Compare 20.7.2. Compare Match Blocking by TCNTn Write 20.7.3. Using the Output Compare Unit 20.8. Compare Match Output Unit 20.8.1. Compare Output Mode and Waveform Generation 20.9. Modes of Operation 20.9.1. Normal Mode 20.9.2. Clear Timer on Compare Match (CTC) Mode 20.9.3. Fast PWM Mode 20.9.4. Phase Correct PWM Mode 20.9.5. Phase and Frequency Correct PWM Mode 20.10. Timer/Counter Timing Diagrams 20.11. Register Description 20.11.1. TCCR1A – Timer/Counter1 Control Register A 20.11.2. TCCR3A – Timer/Counter3 Control Register A 20.11.3. TCCR1B – Timer/Counter1 Control Register B 20.11.4. TCCR3B – Timer/Counter3 Control Register B 20.11.5. TCCR1C – Timer/Counter1 Control Register C 20.11.6. TCCR3C – Timer/Counter3 Control Register C 20.11.7. TCNT1L – Timer/Counter1 Low byte 20.11.8. TCNT1H – Timer/Counter1 High byte 20.11.9. TCNT3L – Timer/Counter3 Low byte 20.11.10. TCNT3H – Timer/Counter3 High byte 20.11.11. OCR1AL – Output Compare Register 1 A Low byte 20.11.12. OCR1AH – Output Compare Register 1 A High byte 20.11.13. OCR1BL – Output Compare Register 1 B Low byte 20.11.14. OCR1BH – Output Compare Register 1 B High byte 20.11.15. OCR1CL – Output Compare Register 1 C Low byte 20.11.16. OCR1CH – Output Compare Register 1 C High byte 20.11.17. OCR3AL – Output Compare Register 3 A Low byte 20.11.18. OCR3AH – Output Compare Register 3 A High byte 20.11.19. OCR3BL – Output Compare Register 3 B Low byte 20.11.20. OCR3BH – Output Compare Register 3 B High byte 20.11.21. OCR3CL – Output Compare Register 3 C Low byte 20.11.22. OCR3CH – Output Compare Register 3 C High byte 20.11.23. ICR1L – Input Capture Register 1 Low byte 20.11.24. ICR1H – Input Capture Register 1 High byte 20.11.25. ICR3L – Input Capture Register 3 Low byte 20.11.26. ICR3H – Input Capture Register 3 High byte 20.11.27. TIMSK – Timer/Counter Interrupt Mask Register 20.11.28. ETIMSK – Extended Timer/Counter Interrupt Mask Register 20.11.29. TIFR – Timer/Counter Interrupt Flag Register 20.11.30. ETIFR – Extended Timer/Counter Interrupt Flag Register 21. 8-bit Timer/Counter0 with PWM and Asynchronous Operation 21.1. Features 21.2. Overview 21.2.1. Registers 21.2.2. Definitions 21.3. Timer/Counter Clock Sources 21.4. Counter Unit 21.5. Output Compare Unit 21.5.1. Force Output Compare 21.5.2. Compare Match Blocking by TCNT0 Write 21.5.3. Using the Output Compare Unit 21.6. Compare Match Output Unit 21.6.1. Compare Output Mode and Waveform Generation 21.7. Modes of Operation 21.7.1. Normal Mode 21.7.2. Clear Timer on Compare Match (CTC) Mode 21.7.3. Fast PWM Mode 21.7.4. Phase Correct PWM Mode 21.8. Timer/Counter Timing Diagrams 21.9. Asynchronous Operation of the Timer/Counter 21.9.1. Asynchronous Operation of Timer/Counter0 21.10. Timer/Counter Prescaler 21.11. Register Description 21.11.1. TCCR0 – Timer/Counter Control Register 21.11.2. TCNT0 – Timer/Counter Register 21.11.3. OCR0 – Output Compare Register 21.11.4. ASSR – Asynchronous Status Register 21.11.5. TIMSK – Timer/Counter Interrupt Mask Register 21.11.6. TIFR – Timer/Counter Interrupt Flag Register 21.11.7. SFIOR – Special Function IO Register 22. 8-bit Timer/Counter2 with PWM 22.1. Features 22.2. Overview 22.2.1. Registers 22.2.2. Definitions 22.3. Timer/Counter Clock Sources 22.4. Counter Unit 22.5. Output Compare Unit 22.5.1. Force Output Compare 22.5.2. Compare Match Blocking by TCNT2 Write 22.5.3. Using the Output Compare Unit 22.6. Compare Match Output Unit 22.6.1. Compare Output Mode and Waveform Generation 22.7. Modes of Operation 22.7.1. Normal Mode 22.7.2. Clear Timer on Compare Match (CTC) Mode 22.7.3. Fast PWM Mode 22.7.4. Phase Correct PWM Mode 22.8. Timer/Counter Timing Diagrams 22.9. Register Description 22.9.1. TCCR2 – Timer/Counter Control Register 22.9.2. TCNT0 – Timer/Counter Register 22.9.3. OCR0 – Output Compare Register 22.9.4. TIMSK – Timer/Counter Interrupt Mask Register 22.9.5. TIFR – Timer/Counter Interrupt Flag Register 23. Output Compare Modulator (OCM1C2) 23.1. Overview 23.2. Description 23.2.1. Timing Example 24. SPI – Serial Peripheral Interface 24.1. Features 24.2. Overview 24.3. SS Pin Functionality 24.3.1. Slave Mode 24.3.2. Master Mode 24.4. Data Modes 24.5. Register Description 24.5.1. SPCR – SPI Control Register 24.5.2. SPSR – SPI Status Register 24.5.3. SPDR – SPI Data Register is a read/write register 25. USART 25.1. Features 25.1.1. Dual USART 25.2. Overview 25.2.1. AVR USART vs. AVR UART – Compatibility 25.3. Clock Generation 25.3.1. Internal Clock Generation – The Baud Rate Generator 25.3.2. Double Speed Operation (U2X) 25.3.3. External Clock 25.3.4. Synchronous Clock Operation 25.4. Frame Formats 25.4.1. Parity Bit Calculation 25.5. USART Initialization 25.6. Data Transmission – The USART Transmitter 25.6.1. Sending Frames with 5 to 8 Data Bits 25.6.2. Sending Frames with 9 Data Bits 25.6.3. Transmitter Flags and Interrupts 25.6.4. Parity Generator 25.6.5. Disabling the Transmitter 25.7. Data Reception – The USART Receiver 25.7.1. Receiving Frames with 5 to 8 Data Bits 25.7.2. Receiving Frames with 9 Data Bits 25.7.3. Receive Compete Flag and Interrupt 25.7.4. Receiver Error Flags 25.7.5. Parity Checker 25.7.6. Disabling the Receiver 25.7.7. Flushing the Receive Buffer 25.8. Asynchronous Data Reception 25.8.1. Asynchronous Clock Recovery 25.8.2. Asynchronous Data Recovery 25.8.3. Asynchronous Operational Range 25.9. Multi-Processor Communication Mode 25.9.1. Using MPCM 25.10. Examples of Baud Rate Setting 25.11. Register Description 25.11.1. UDRn – USART I/O Data Register 25.11.2. UCSRmA – USART Control and Status Register A 25.11.3. UCSRmB – USART Control and Status Register B 25.11.4. UCSRmC – USART Control and Status Register C 25.11.5. UBRRmL – USART Baud Rate Register Low 25.11.6. UBBRmH – USART Baud Rate Register High 26. TWI - Two-wire Serial Interface 26.1. Features 26.2. Overview 26.2.1. SCL and SDA Pins 26.2.2. Bit Rate Generator Unit 26.2.3. Bus Interface Unit 26.2.4. Address Match Unit 26.2.5. Control Unit 26.3. Two-Wire Serial Interface Bus Definition 26.3.1. TWI Terminology 26.3.2. Electrical Interconnection 26.4. Data Transfer and Frame Format 26.4.1. Transferring Bits 26.4.2. START and STOP Conditions 26.4.3. Address Packet Format 26.4.4. Data Packet Format 26.4.5. Combining Address and Data Packets Into a Transmission 26.5. Multi-master Bus Systems, Arbitration and Synchronization 26.6. Using the TWI 26.6.1. Transmission Modes 26.6.2. Master Transmitter Mode 26.6.3. Master Receiver Mode 26.6.4. Slave Receiver Mode 26.6.5. Slave Transmitter Mode 26.6.6. Miscellaneous States 26.6.7. Combining Several TWI Modes 26.7. Multi-master Systems and Arbitration 26.8. Register Description 26.8.1. TWBR – TWI Bit Rate Register 26.8.2. TWCR – TWI Control Register 26.8.3. TWSR – TWI Status Register 26.8.4. TWDR – TWI Data Register 26.8.5. TWAR – TWI (Slave) Address Register 27. Analog Comparator 27.1. Overview 27.2. Analog Comparator Multiplexed Input 27.3. Register Description 27.3.1. SFIOR – Analog Comparator Control and Status Register 27.3.2. ACSR – Analog Comparator Control and Status Register 28. ADC - Analog to Digital Converter 28.1. Features 28.2. Overview 28.3. Starting a Conversion 28.4. Prescaling and Conversion Timing 28.4.1. Differential Gain Channels 28.5. Changing Channel or Reference Selection 28.5.1. ADC Input Channels 28.5.2. ADC Voltage Reference 28.6. ADC Noise Canceler 28.6.1. Analog Input Circuitry 28.6.2. Analog Noise Canceling Techniques 28.6.3. Offset Compensation Schemes 28.6.4. ADC Accuracy Definitions 28.7. ADC Conversion Result 28.8. Register Description 28.8.1. ADMUX – ADC Multiplexer Selection Register 28.8.2. ADCSRA – ADC Control and Status Register A 28.8.3. ADCL – ADC Data Register Low (ADLAR=0) 28.8.4. ADCH – ADC Data Register High (ADLAR=0) 28.8.5. ADCL – ADC Data Register Low (ADLAR=1) 28.8.6. ADCH – ADC Data Register High (ADLAR=1) 28.8.7. ADCSRB – ADC Control and Status Register B 29. JTAG Interface and On-chip Debug System 29.1. Features 29.2. Overview 29.3. TAP – Test Access Port 29.4. TAP Controller 29.5. Using the Boundary-scan Chain 29.6. Using the On-chip Debug System 29.7. On-chip Debug Specific JTAG Instructions 29.8. Using the JTAG Programming Capabilities 29.9. Bibliography 29.10. IEEE 1149.1 (JTAG) Boundary-scan 29.10.1. Features 29.10.2. System Overview 29.11. Data Registers 29.11.1. Bypass Register 29.11.2. Device Identification Register 29.11.2.1. Version 29.11.2.2. Part Number 29.11.2.3. Manufacturer ID 29.11.3. Reset Register 29.11.4. Boundary-scan Chain 29.12. Boundry-scan Specific JTAG Instructions 29.12.1. EXTEST; 0x0 29.12.2. IDCODE; 0x1 29.12.3. SAMPLE_PRELOAD; 0x2 29.12.4. AVR_RESET; 0xC 29.12.5. BYPASS; 0xF 29.13. Boundary-scan Chain 29.13.1. Scanning the Digital Port Pins 29.13.2. Boundary-scan and the Two-wire Interface 29.13.3. Scanning the RESET Pin 29.13.4. Scanning the Clock Pins 29.13.5. Scanning the Analog Comparator 29.13.6. Scanning the ADC 29.14. ATmega64A Boundary-scan Order 29.15. Boundary-scan Description Language Files 29.16. Register Description 29.16.1. OCDR – On-chip Debug Register 29.16.2. MCUCSR – MCU Control and Status Register 30. BTLDR - Boot Loader Support – Read-While-Write Self-Programming 30.1. Features 30.2. Overview 30.3. Application and Boot Loader Flash Sections 30.3.1. Application Section 30.3.2. BLS – Boot Loader Section 30.4. Read-While-Write and No Read-While-Write Flash Sections 30.4.1. RWW – Read-While-Write Section 30.4.2. NRWW – No Read-While-Write Section 30.5. Boot Loader Lock Bits 30.6. Entering the Boot Loader Program 30.7. Addressing the Flash During Self-Programming 30.8. Self-Programming the Flash 30.8.1. Performing Page Erase by SPM 30.8.2. Filling the Temporary Buffer (Page Loading) 30.8.3. Performing a Page Write 30.8.4. Using the SPM Interrupt 30.8.5. Consideration While Updating Boot Loader Section (BLS) 30.8.6. Prevent Reading the RWW Section During Self-Programming 30.8.7. Setting the Boot Loader Lock Bits by SPM 30.8.8. EEPROM Write Prevents Writing to SPMCSR 30.8.9. Reading the Fuse and Lock Bits from Software 30.8.10. Preventing Flash Corruption 30.8.11. Programming Time for Flash when Using SPM 30.8.12. Simple Assembly Code Example for a Boot Loader 30.8.13. ATmega64A Boot Loader Parameters 30.9. Register Description 30.9.1. SPMCSR – Store Program Memory Control and Status Register 31. Memory Programming 31.1. Program and Data Memory Lock Bits 31.2. Fuse Bits 31.2.1. Latching of Fuses 31.3. Signature Bytes 31.4. Calibration Byte 31.5. Page Size 31.6. Parallel Programming 31.6.1. Enter Programming Mode 31.6.2. Considerations for Efficient Programming 31.6.3. Chip Erase 31.6.4. Programming the Flash 31.6.5. Programming the EEPROM 31.6.6. Reading the Flash 31.6.7. Reading the EEPROM 31.6.8. Programming the Fuse Low Bits 31.6.9. Programming the Fuse High Bits 31.6.10. Programming the Extended Fuse Bits 31.6.11. Programming the Lock Bits 31.6.12. Reading the Fuse and Lock Bits 31.6.13. Reading the Signature Bytes 31.6.14. Reading the Calibration Byte 31.6.15. Parallel Programming Characteristics 31.7. Parallel Programming Parameters, Pin Mapping, and Commands 31.7.1. Signal Names 31.8. Serial Downloading 31.9. Serial Programming Pin Mapping 31.9.1. SPI Serial Programming Algorithm 31.9.2. Data Polling Flash 31.9.3. Data Polling EEPROM 31.9.4. SPI Serial Programming Characteristics 31.10. Programming Via the JTAG Interface 31.10.1. Programming Specific JTAG Instructions 31.10.2. AVR_RESET (0xC) 31.10.3. PROG_ENABLE (0x4) 31.10.4. PROG_COMMANDS (0x5) 31.10.5. PROG_PAGELOAD (0x6) 31.10.6. PROG_PAGEREAD (0x7) 31.10.7. Data Registers 31.10.8. Reset Register 31.10.9. Programming Enable Register 31.10.10. Programming Command Register 31.10.11. Virtual Flash Page Load Register 31.10.12. Virtual Flash Page Read Register 31.10.13. Programming Algorithm 31.10.14. Entering Programming Mode 31.10.15. Leaving Programming Mode 31.10.16. Performing Chip Erase 31.10.17. Programming the Flash 31.10.18. Reading the Flash 31.10.19. Programming the EEPROM 31.10.20. Reading the EEPROM 31.10.21. Programming the Fuses 31.10.22. Programming the Lock Bits 31.10.23. Reading the Fuses and Lock Bits 31.10.24. Reading the Signature Bytes 31.10.25. Reading the Calibration Byte 32. Electrical Characteristics – TA = -40°C to 85°C 32.1. DC Characteristics 32.2. Speed Grades 32.3. Clock Characteristics 32.3.1. External Clock Drive Waveforms 32.3.2. External Clock Drive 32.4. System and Reset Characteristics 32.5. Two-wire Serial Interface Characteristics 32.6. Parallel Programming Characteristics 32.7. SPI Timing Characteristics 32.8. ADC Characteristics 32.9. External Data Memory Timing 33. Electrical Characteristics – TA = -40°C to 105°C 33.1. DC Characteristics 34. Typical Characteristics – TA = -40°C to 85°C 34.1. Active Supply Current 34.2. Idle Supply Current 34.3. Power-Down Supply Current 34.4. Power-Save Supply Current 34.5. Standby Supply Current 34.6. Pin Pull-up 34.7. Pin Driver Strength 34.8. Pin Thresholds and Hysteresis 34.9. BOD Thresholds and Analog Comparator Offset 34.10. Internal Oscillator Speed 34.11. Current Consumption of Peripheral Units 34.12. Current Consumption in Reset and Reset Pulse width 35. Typical Characteristics – TA = -40°C to 105°C 35.1. Active Supply Current 35.2. Idle Supply Current 35.3. Power-down Supply Current 35.4. Pin Pull-up 35.5. Pin Driver Strength 35.6. Pin Thresholds and Hysteresis 35.7. BOD Thresholds and Analog Comparator Offset 35.8. Internal Oscillator Speed 35.9. Current Consumption of Peripheral Units 35.10. Current Consumption in Reset and Reset Pulsewidth 36. Register Summary 37. Instruction Set Summary 38. Packaging Information 38.1. 64A 38.2. 64M1 39. Errata 39.1. ATmega64A Rev. D 40. Datasheet Revision History 40.1. 8160E - 07/2015 40.2. 8160D - 02/2013 40.3. 8160C - 07/2009 40.4. 8160B - 03/2009 40.5. 8160A - 08/2008