Datasheet AD537 (Analog Devices) - 5

AD537 NONLINEARITY SPECIFICATION
Figure 5 shows the AD537 with a standard 0 to +10 volt input The preferred method for specifying linearity error is in terms of connection and the output stage connections. The values for the the maximum deviation from the ideal relationship after cali- logic common voltage, pull-up resistor, positive logic level, and brating the converter at full scale and “zero”. This error will –VS supply are given in the accompanying chart for several logic vary with the full-scale frequency and the mode of operation. forms. The AD537 operates best at a 10 kHz full-scale frequency with a negative voltage input; the linearity is typically within ± 0.05%.
LOGIC COM VEE
Operating at higher frequencies or with positive inputs will
AD537 f
degrade the linearity as indicates in the Specification table. The
1 14 OUT RL LOGIC VCC
shape of a typical linearity plot is given in Figure 4.
2 13 DRIVER +VS (+15V) 3 12 10k CURR- C V V R 0.18 CC EE L –VS BUF 4 TO-FREQ 11 TTL/DTL +5 GND 5k GND 0.16 TEST CONDITIONS: CONV +V V 5V CMOS +5 GND 20k GND IN 5 10 0.14 S = +15V –V 15V CMOS/ +15 GND 10k GND S = 0V 0.12 AD537J C V HNIL T = 0.01µF 6 V 9 OS T PRECISION R 20k ECL 10k 0 –8 5k –8 TO VOLTAGE 0.10 T = 10k
Ω
V VR REFERENCE 8 FS =
±
10V 7 –VS –15 0.08 POS INPUT – FIG. 3 ECL2.5k +1.3 –2 5k –5 NEG INPUT – FIG. 4 0.06 PMOS 0 –15 10k –15 % OF FULL SCALE – 0.04 0.02
Figure 5. Interfacing Standard Logic Families
0 –0.02 APPLICATIONS AD537K, S
The diagrams and descriptions of the following applications are
NONLINEARITY –0.04 –0.06
provided to stimulate the discerning engineer with alternative
–0.08
circuit design ideas. “Applications of the AD537 IC Voltage-
1 10 100 1k 10k
to-Frequency Converter”, available from Analog Devices on
OUTPUT FREQUENCY – Hz
request, covers a wider range of topics and concepts in data conversion and data transmission using voltage-to-frequency Figure 4a. Typical Nonlinearity Error Envelopes with converters. 10 kHz F.S. Output
TRUE TWO-WIRE DATA TRANSMISSION 0.18
Figure 6 shows the AD537 in a true two-wire data transmission
0.16 TEST CONDITIONS: +V
scheme. The twisted-pair transmission lines serves the dual pur-
0.14 S = +15V –VS = 0V
pose of supplying power to the device and also carrying fre-
0.12 CT = 0.001µF AD537J R
quency data in the form of current modulation. The PNP circuit
0.10 T = 10k
Ω
VFS =
±
10V
at the receiving end represents a fairly simple way for converting
0.08 POS INPUT – FIG. 3 NEG INPUT – FIG. 4
the current modulation back into a voltage square wave which
0.06 % OF FULL SCALE
will drive digital logic directly. The 0.6 volt square wave which
– 0.04
will appear on the supply line at the device terminals does not
0.02 0
affect the performance of the AD537 because of its excellent
AD537K, S
supply rejection. Also, note that the circuit operates at nearly
–0.02
constant average power regardless of frequency.
NONLINEARITY –0.04 –0.06 –0.08 LOGIC GND 10 100 1k 10k 100k 10 R R OUTPUT FREQUENCY – Hz CAL SCALE 1 9 RL V AD537 IN
Figure 4b. Typical Nonlinearity Error with 100 kHz F.S.
DRIVER +VS 120
Output
+V +V IN 2 8 S CURR- TO-FREQ OUTPUT INTERFACING CONSIDERATIONS BUF CONV
The design of the output stage allows easy interfacing to all digi-
V 3 TEMP 7 V R T PRECISION S
tal logic families. The collector and emitter of the output NPN
VOLTAGE V OUTPUT R REFERENCE C
transistor are both uncommitted; the emitter can be tied to any
TWO-WIRE V 220
Ω
REF 4 6 LINK
voltage between –VS and 4 volts below +VS. The open collector
5
can be pulled up to a voltage 36 volts above the emitter regard-
–VS VS RS RL
less of +V
(CONNECTED TO CASE) +5 0 1k
S. The high power output stage can supply up to
+15 1k 3.3k
20 mA (10 mA for “H” package) at a maximum saturation volt- age of 0.4 volts. The stage limits the output current at 25 mA; it Figure 6. True Two-Wire Operation can handle this limit indefinitely without damaging the device. REV. C –5–