Datasheet AD537 (Analog Devices) - 4

AD537
In some cases the signal may be in the form of a negative cur- The –VIN, +VIN and IIN pins should not be driven more than rent source. This can be handled in a similar way to a negative 300 mV below –VS. This would cause internal junctions to con- input voltage. However, the scaling resistor is no longer re- duct, possibly damaging the IC. The AD537 can be protected quired, eliminating the capability of trimming full scale in this from “below –VS” inputs by a Schottky diode, CR1 (HP5082- fashion. Since it will usually be impractical to vary the capaci- 2811) as shown in Figure 3. It is also desirable not to drive tance, an alternative calibration scheme is needed. This is +VIN, –VIN and IIN above +VS. In operation, the converter will shown in Figure 3. A resistor-potentiometer connected from become very nonlinear for inputs above (+VS – 3.5 V). Control the VR output to –VS will alter the internal operating conditions currents above 2 mA will also cause nonlinearity. in a predictable way, providing the necessary adjustment range. The 80 dB dynamic range of the AD537 guarantees operation With the values shown, a range of ± 4% is available; a larger from a control current of 1 mA (nominal FS) down to 100 nA range can be attained by reducing R1. This technique does not (equivalent to 1 mV to 10 V FS). Below 100 nA improper op- degrade the temperature-coefficient of the converter, and the eration of the oscillator may result, causing a false indication of linearity will be as for negative input voltages. The minimum input amplitude. In many cases this might be due to short-lived supply voltage may be used. noise spikes which become added to the input. For example, Unless it is required to set the input node at exactly ground when scaled to accept a FS input of 1 V, the –80 dB level is potential, no offset adjustment is needed. The capacitor C is se- only 100 µV, so when the mean input is only 60 dB below FS lected to be 5% below the nominal value; with R2 in its (1 mV), noise spikes of 0.9 mV are sufficient to cause momen- midposition the output frequency is given by: tary malfunction. This effect can be minimized by using a simple low-pass filter f = I ahead of the converter and a guard ring around the IIN or –VIN 10.5 × C pins. For a FS of 10 kHz a single-pole filter with a time-constant where f is in kHz, I is in mA and C is in µF. For example, for a of 100 ms (Figure 2) will be suitable, but the optimum configu- FS frequency of 10 kHz at a FS input of 1 mA, C = 9500 pF. ration will depend on the application and type of signal process- Calibration is effected by applying the full-scale input and ad- ing. Noise spikes are only likely to be a cause of error when the justing R2 for the correct reading. input current remains near its minimum value for long periods of time; above 100 nA (1 mV) full integration of additive input This alternative adjustment scheme may also be used when it is noise occurs. desired to present an exact input resistance in the negative volt- age mode. The scaling relationship is then The AD537 is somewhat susceptible to interference from other signals. The most sensitive nodes (besides the inputs) are the f = V × 1 capacitor terminals and the SYNC pin. The timing capacitor R 10.5 C EXACT should be located as close as possible to the AD537 to minimize signal pickup in the leads. In some cases, guard rings or shield- The calibration procedure is then similar to that used for posi- ing may be required. The SYNC pin should be decoupled tive input voltages, except that the scale adjustment is by means through a 0.005 of R2. µF (or larger) capacitor to Pin 13 (+VS). This minimizes the possibility that the AD537 will attempt to syn-
VLOGIC
chronize to a spurious signal. This precaution is unnecessary on the metal can package since the SYNC function is not brought
AD537 OUTPUT
out to a package pin and is thus not susceptible to pickup.
LOGIC GND 1 14 IIN f = DEC/SYN 2 DRIVER 13 +VS 10C DECOUPLING
It is good engineering practice to use bypass capacitors on the
3 12 I CURR- CAP C BUF
supply-voltage pins and to insert small-valued resistors (10 Ω to
IIN 4 TO-FREQ 11 CONV
100 Ω) in the supply lines to provide a measure of decoupling
V 5 10 VOS
between the various circuits in a system. Ceramic capacitors of
VTEMP 6 V PRECISION 9 V T OS
0.1 µF to 1.0 µF should be applied between the supply-voltage
V VOLTAGE REF V
pins and analog signal ground for proper bypassing on the
7 R REFERENCE 8 –VS R1
AD537.
27k R2 ADJ.
A decoupling capacitor may also be useful from +VS to SYNC
200k SCALE
in those applications where very low cycle-to-cycle period varia- tion (jitter) is demanded. By placing a capacitor across +VS and Figure 3. Scale Adjustment for Current Inputs SYNC this noise is reduced. On the 10 kHz FS range, a 6.8 µF capacitor reduces the jitter to one in 20,000 which adequate for
INPUT PROTECTION
most applications. A tantalum capacitor should be used to avoid The AD537 was designed to be used with a minimum of addi- errors due to dc leakage. tional hardware. However, the successful application of a preci- sion IC involves a good understanding of possible pitfalls and the use of suitable precautions. –4– REV. C