Datasheet LTC3459 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | 10V Micropower Synchronous Boost Converter in ThinSOT |
| Páginas / Página | 12 / 6 — PIN FUNCTIONS (DC/DCB/S6 Packages). VIN (Pin 1/Pin 6/Pin 6):. GND (Pin … |
| Formato / tamaño de archivo | PDF / 226 Kb |
| Idioma del documento | Inglés |
PIN FUNCTIONS (DC/DCB/S6 Packages). VIN (Pin 1/Pin 6/Pin 6):. GND (Pin 5/Pin 5/Pin 2):. OUT (Pin 2/Pin 2/Pin 5):
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LTC3459
PIN FUNCTIONS (DC/DCB/S6 Packages) VIN (Pin 1/Pin 6/Pin 6):
Input Supply Pin. Bypass VIN with
GND (Pin 5/Pin 5/Pin 2):
Signal and Power Ground. Provide a low ESR, ESL ceramic capacitor of at least 1μF. a short, direct PCB path between GND and the (–) side of the fi lter capacitors on V
V
IN and VOUT.
OUT (Pin 2/Pin 2/Pin 5):
Regulated Output Voltage of the Boost Regulator. Bypass VOUT with a low ESR, ESL
SW (Pin 6/Pin 4/Pin 1):
Switch Pin. Connect a 15μH to ceramic capacitor between 2.2μF and 10μF. VOUT ripple 33μH inductor between SW and VIN. Keep PCB trace lengths increases with smaller capacitors. as short and wide as possible to reduce EMI and voltage
SHDN
overshoot. If the inductor current falls to zero, the internal
(Pin 3/Pin 1/Pin 4):
Master Shutdown Input. Driving SHDN P-channel MOSFET synchronous rectifi er is turned off to low disables all IC functions and reduces quiescent prevent reverse charging of the inductor. current from the battery to less than 1μA. This pin must be pulled above 1V to enable the IC.
Exposed Pad (Pin 7/Pin 7, DC and DCB Packages Only):
Ground. The Exposed Pad must be soldered to PCB.
FB (Pin 4/Pin 3/Pin 3):
Input to the Burst Mode Comparator. An external resistor divider connected between VOUT, GND and this pin sets the output voltage to: VOUT = 1.22(1 + R1/R2)
BLOCK DIAGRAM
VCC SW – VIN V t SELECT OFF t V OFF OUT TIMER + IPEAK Q SD I SW1 ZO VBEST QB R IZERO DETECT Q S P/~N VOUT QB RD THERMAL SLEEP SD DELAY V P-DRIVE SELECT IZO S Q R1 RD QB – FB VCC VBEST R2 I HYSTCOMP + PEAK DETECT VCC N-DRIVE REFOK SDB N-DRIVE REFERENCE P-DRIVE SD SD SDB GND SHDN 3459 BD OFF ON 3459fc 6
PIN FUNCTIONS (DC/DCB/S6 Packages) VIN (Pin 1/Pin 6/Pin 6):
Input Supply Pin. Bypass VIN with
GND (Pin 5/Pin 5/Pin 2):
Signal and Power Ground. Provide a low ESR, ESL ceramic capacitor of at least 1μF. a short, direct PCB path between GND and the (–) side of the fi lter capacitors on V
V
IN and VOUT.
OUT (Pin 2/Pin 2/Pin 5):
Regulated Output Voltage of the Boost Regulator. Bypass VOUT with a low ESR, ESL
SW (Pin 6/Pin 4/Pin 1):
Switch Pin. Connect a 15μH to ceramic capacitor between 2.2μF and 10μF. VOUT ripple 33μH inductor between SW and VIN. Keep PCB trace lengths increases with smaller capacitors. as short and wide as possible to reduce EMI and voltage
SHDN
overshoot. If the inductor current falls to zero, the internal
(Pin 3/Pin 1/Pin 4):
Master Shutdown Input. Driving SHDN P-channel MOSFET synchronous rectifi er is turned off to low disables all IC functions and reduces quiescent prevent reverse charging of the inductor. current from the battery to less than 1μA. This pin must be pulled above 1V to enable the IC.
Exposed Pad (Pin 7/Pin 7, DC and DCB Packages Only):
Ground. The Exposed Pad must be soldered to PCB.
FB (Pin 4/Pin 3/Pin 3):
Input to the Burst Mode Comparator. An external resistor divider connected between VOUT, GND and this pin sets the output voltage to: VOUT = 1.22(1 + R1/R2)
BLOCK DIAGRAM
VCC SW – VIN V t SELECT OFF t V OFF OUT TIMER + IPEAK Q SD I SW1 ZO VBEST QB R IZERO DETECT Q S P/~N VOUT QB RD THERMAL SLEEP SD DELAY V P-DRIVE SELECT IZO S Q R1 RD QB – FB VCC VBEST R2 I HYSTCOMP + PEAK DETECT VCC N-DRIVE REFOK SDB N-DRIVE REFERENCE P-DRIVE SD SD SDB GND SHDN 3459 BD OFF ON 3459fc 6