Datasheet LT1072 - 8

LT1072
U LT1072 OPERATIO
rough guide to calculate LT1072 power dissipation. For The third approach for lower current applications is to more details, the reader is referred to Application Note 19 leave the second switch emitter open. This increases (AN19), “Efficiency Calculations” section. switch “on” resistance by 2:1, but reduces switch current limit by 2:1 also, resulting in a net 2:1 reduction in I2R Average supply current (including driver current) is: switch dissipation under current limit conditions. IIN ≈ 6mA + ISW(0.004 + DC/40) The fourth approach is to clamp the VC pin to a voltage less ISW = switch current than its internal clamp level of 2V. The LT1072 switch DC = switch duty cycle current limit is zero at approximately 1V on the VC pin and Switch power dissipation is given by: 2A at 2V on the VC pin. Peak switch current can be externally clamped between these two levels with a diode. PSW = (ISW)2 • RSW • DC See AN-19 for details. RSW = LT1072 switch “on” resistance (1Ω maximum)
LT1072 Synchronizing
Total power dissipation is the sum of supply current times input voltage plus switch power: The LT1072 can be externally synchronized in the frequency range of 48kHz to 70kHz. This is accomplished as shown PTOT = (llN)(VIN) + PSW in the accompanying figures. Synchronizing occurs when In a typical example, using a boost converter to generate the VC pin is pulled to ground with an external transistor. 12V @ 0.12A from a 5V input, duty cycle is approximately To avoid disturbing the DC characteristics of the internal 60%, and switch current is about 0.65A, yielding: error amplifier, the width of the synchronizing pulse should be under 1µs. C2 sets the pulse width at ≈ 0.35µs. llN = 6mA + 0.65(0.004 + DC/40) = 18mA The effect of a synchronizing pulse on the LT1072 PSW = (0.65)2 • 1Ω • (0.6) = 0.25W amplifier offset can be calculated from: P KT TOT = (5V)(0.018A) + 0.25 = 0.34W (t ( VC S)(fS) I ( C + ( q ∆V R3 OS = Temperature rise in a plastic miniDIP would be 130°C/W IC times 0.34W, or approximately 44°C. The maximum KT ambient temperature would be limited to 100°C = 26mV at 25°C q (commercial temperature limit) minus 44°C, or 56°C. tS = pulse width In most applications, full load current is used to calculate fS = pulse frequency die temperature. However, if overload conditions must IC = LT1072 VC source current (≈ 200µA) also be accounted for, four approaches are possible. First, VC = LT1072 operating VC voltage (1V to 2V) if loss of regulated output is acceptable under overload R3 = resistor used to set mid-frequency “zero” in LT1072 conditions, the internal thermal limit of the LT1072 will frequency compensation network. protect the die in most applications by shutting off switch current. Thermal limit is not a tested parameter, however, With tS = 0.35µs, fS = 50kHz, VC = 1.5V, and R3 = 2KΩ, and should be considered only for non-critical applications offset voltage shift is ≈2.2mV. This is not particularly with temporary overloads. A second approach is to use the bothersome, but note that high offsets could result larger TO-220 (T) or TO-3 (K) package which, even without if R3 were reduced to a much lower value. Also, the a heat sink, may limit die temperatures to safe levels under synchronizing transistor must sink higher currents with overload conditions. In critical situations, heat sinking low values of R3, so larger drives may have to be used. The of these packages is required; especially if overload transistor must be capable of pulling the VC pin to within conditions must be tolerated for extended periods of time. 200mV of ground to ensure synchronizing. 1072fc 8