Datasheet ADP5034 (Analog Devices)

Dual 3 MHz, 1200 mA Buck Regulators with Two 300 mA LDOs Data Sheet ADP5034 FEATURES
regulators operate in PWM mode when the load is above a pre-
Main input voltage range: 2.3 V to 5.5 V
defined threshold. When the load current falls below a predefined
Two 1200 mA buck regulators and two 300 mA LDOs
threshold, the regulator operates in power save mode (PSM),
24-lead, 4 mm × 4 mm LFCSP or 28-lead TSSOP package
improving the light load efficiency.
Regulator accuracy: ±1.8% Table 1. Family Models Factory programmable or external adjustable VOUTx Maximum 3 MHz buck operation with forced PWM and auto PWM/PSM Model Channels Current Package modes
ADP5023 2 Buck,1 LDO 800 mA, LFCSP (CP-24-10)
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
300 mA
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
ADP5024 2 Buck,1 LDO 1.2 A, LFCSP (CP-24-10) 300 mA
LDO1/LDO2: input supply voltage from 1.7 V to 5.5 V
ADP5034 2 Buck,2 LDOs 1.2 A, LFCSP (CP-24-10),
LDO1/LDO2: high PSRR and low output noise
300 mA TSSOP (RE-28-1)
APPLICATIONS
ADP5037 2 Buck,2 LDOs 800 mA, LFCSP (CP-24-10) 300 mA
Power for processors, ASICS, FPGAs, and RF chipsets
ADP5033 2 Buck,2 LDOs with 800 mA, WLCSP (CB-16-8)
Portable instrumentation and medical devices
2 EN pins 300 mA
Space constrained devices
The two bucks operate out of phase to reduce the input capaci-
GENERAL DESCRIPTION
tor requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5034 LDOs extend the The ADP5034 combines two high performance buck regulators battery life of portable devices. The ADP5034 LDOs maintain and two low dropout (LDO) regulators. It is available in either a power supply rejection greater than 60 dB for frequencies as 24-lead 4 mm × 4 mm LFCSP or a 28-lead TSSOP package. high as 10 kHz while operating with a low headroom voltage. The high switching frequency of the buck regulators enables tiny Regulators in the ADP5034 are activated through dedicated multilayer external components and minimizes the board space. enable pins. The default output voltages can be externally set in When the MODE pin is set to high, the buck regulators operate in the adjustable version, or factory programmable to a wide range forced PWM mode. When the MODE pin is set to low, the buck of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT AVIN HOUSEKEEPING CAVIN VOUT1 0.1µF L1 1µH VIN1 2.3V TO SW1 VOUT1 AT 5.5V C1 1200mA FB1 R1 4.7µF BUCK1 C5 R2 10µF ON EN1 PGND1 EN1 OFF MODE PWM MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH C2 SW2 VOUT2 AT 4.7µF 1200mA BUCK2 FB2 R3 C6 EN2 EN2 R4 PGND2 10µF EN3 VOUT3 VOUT3 AT EN3 LDO1 300mA VIN3 R5 1.7V TO (ANALOG) FB3 C7 5.5V C3 R6 1µF 1µF EN4 ON VOUT4 V EN4 OUT4 AT OFF 300mA LDO2 R7 VIN4 FB4 (DIGITAL) C8 C4 R8 1µF 1µF ADP5034
001
AGND
09703- Figure 1.
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Document Outline Features Applications General Description Typical Application Circuit Revision History Specifications General Specifications BUCK1 and BUCK2 Specifications LDO1 and LDO2 Specifications Input and Output Capacitor, Recommended Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Management Unit Thermal Protection Undervoltage Lockout Enable/Shutdown BUCK1 and BUCK2 Control Scheme PWM Mode Power Save Mode (PSM) PSM Current Threshold Oscillator/Phasing of Inductor Switching Short-Circuit Protection Soft Start Current Limit 100% Duty Operation Active Pull-Downs LDO1 and LDO2 Applications Information Buck External Component Selection Feedback Resistors Inductor Output Capacitor Input Capacitor LDO External Component Selection Feedback Resistors Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties Power Dissipation and Thermal Considerations Buck Regulator Power Dissipation LDO Regulator Power Dissipation Junction Temperature PCB Layout Guidelines Typical Application Schematics Bill of Materials Outline Dimensions Ordering Guide