Datasheet LTC1392 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | Micropower Temperature, Power Supply and Differential Voltage Monitor |
| Páginas / Página | 12 / 3 — ELECTRICAL CHAR C. A TERISTICS (Note 2, 3). SYMBOL. PARAMETER. … |
| Formato / tamaño de archivo | PDF / 259 Kb |
| Idioma del documento | Inglés |
ELECTRICAL CHAR C. A TERISTICS (Note 2, 3). SYMBOL. PARAMETER. CONDITIONS. MIN. TYP. MAX. UNITS. RECOM ENDED OPERATING CONDITIONS
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LTC1392
ELECTRICAL CHAR C A TERISTICS (Note 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ION LEAKAGE On-Channel Leakage Current (Note 6) ● ±1 µA IOFF LEAKAGE Off-Channel Leakage Current (Note 6) ● ±1 µA VIH High Level Input Voltage VCC = 5.25V ● 2 V VIL Low Level Input Voltage VCC = 4.75V ● 0.8 V IIH High Level Input Current VIN = VCC ● 5 µA IIL Low Level Input Current VIN = 0V ● – 5 µA VOH High Level Output Voltage VCC = 4.75V, IOUT = 10µA ● 4.5 4.74 V VCC = 4.75V, IOUT = 360µA 2.4 4.72 V VOL Low Level Output Voltage VCC = 4.75V, IOUT = 1.6mA ● 0.4 V IOZ Hi-Z Output Current CS = High ● ±5 µA ISOURCE Output Source Current VOUT = 0V – 25 mA ISINK Output Sink Current VOUT = VCC 45 mA ICC Supply Current CS = High ● 0.1 5 µA CS = Low, VCC = 5V ● 0.7 1 mA tSMPL Analog Input Sample Time See Figure 1 1.5 CLK Cycles tCONV Conversion Time See Figure 1 10 CLK Cycles tdDO Delay Time, CLK↓ to DOUT Data Valid CLOAD = 100pF ● 150 300 ns ten Delay Time, CLK↓ to DOUT Data Enabled CLOAD = 100pF ● 60 150 ns tdis Delay Time, CS ↑ to DOUT Hi-Z ● 170 450 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 30 ns tf DOUT Fall Time CLOAD = 100pF ● 70 250 ns tr DOUT Rise Time CLOAD = 100pF ● 25 100 ns CIN Input Capacitance Analog Input On-Channel 30 pF Analog Input Off-Channel 5 pF Digital Input 5 pF
WW U U U U RECOM ENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 4.5 6 V fCLK Clock Frequency VCC = 5V 150 250 350 kHz tCYC Total Cycle Time fCLK = 250kHz 74 µs Temperature Conversion Only 144 µs thDI Hold Time, DIN After CLK↑ VCC = 5V 150 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Figure 1) VCC = 5V 2 µs tWAKEUP Wakeup Time CS↓ Before Start Bit↑ (See Figure 1) VCC = 5V 10 µs Temperature Conversion Only 80 µs tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 5V 150 ns tWHCLK Clock High Time VCC = 5V 1.6 µs tWLCLK Clock Low Time VCC = 5V 2 µs tWHCS CS High Time Between Data Transfer Cycles VCC = 5V, fCLK = 250kHz 2 µs tWLCS CS Low Time During Data Transfer VCC = 5V, fCLK = 250kHz 72 µs Temperature Conversion Only 142 µs 3
ELECTRICAL CHAR C A TERISTICS (Note 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ION LEAKAGE On-Channel Leakage Current (Note 6) ● ±1 µA IOFF LEAKAGE Off-Channel Leakage Current (Note 6) ● ±1 µA VIH High Level Input Voltage VCC = 5.25V ● 2 V VIL Low Level Input Voltage VCC = 4.75V ● 0.8 V IIH High Level Input Current VIN = VCC ● 5 µA IIL Low Level Input Current VIN = 0V ● – 5 µA VOH High Level Output Voltage VCC = 4.75V, IOUT = 10µA ● 4.5 4.74 V VCC = 4.75V, IOUT = 360µA 2.4 4.72 V VOL Low Level Output Voltage VCC = 4.75V, IOUT = 1.6mA ● 0.4 V IOZ Hi-Z Output Current CS = High ● ±5 µA ISOURCE Output Source Current VOUT = 0V – 25 mA ISINK Output Sink Current VOUT = VCC 45 mA ICC Supply Current CS = High ● 0.1 5 µA CS = Low, VCC = 5V ● 0.7 1 mA tSMPL Analog Input Sample Time See Figure 1 1.5 CLK Cycles tCONV Conversion Time See Figure 1 10 CLK Cycles tdDO Delay Time, CLK↓ to DOUT Data Valid CLOAD = 100pF ● 150 300 ns ten Delay Time, CLK↓ to DOUT Data Enabled CLOAD = 100pF ● 60 150 ns tdis Delay Time, CS ↑ to DOUT Hi-Z ● 170 450 ns thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 30 ns tf DOUT Fall Time CLOAD = 100pF ● 70 250 ns tr DOUT Rise Time CLOAD = 100pF ● 25 100 ns CIN Input Capacitance Analog Input On-Channel 30 pF Analog Input Off-Channel 5 pF Digital Input 5 pF
WW U U U U RECOM ENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 4.5 6 V fCLK Clock Frequency VCC = 5V 150 250 350 kHz tCYC Total Cycle Time fCLK = 250kHz 74 µs Temperature Conversion Only 144 µs thDI Hold Time, DIN After CLK↑ VCC = 5V 150 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Figure 1) VCC = 5V 2 µs tWAKEUP Wakeup Time CS↓ Before Start Bit↑ (See Figure 1) VCC = 5V 10 µs Temperature Conversion Only 80 µs tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 5V 150 ns tWHCLK Clock High Time VCC = 5V 1.6 µs tWLCLK Clock Low Time VCC = 5V 2 µs tWHCS CS High Time Between Data Transfer Cycles VCC = 5V, fCLK = 250kHz 2 µs tWLCS CS Low Time During Data Transfer VCC = 5V, fCLK = 250kHz 72 µs Temperature Conversion Only 142 µs 3