Datasheet ACT 1 (Actel) - 7

A C T ™ 1 S e r i e s F P G A s P a c k a g e T h e r m a l C h a r a c t e r i s t i c s
A sample calculation of the maximum power dissipation for The device junction to case thermal characteristics is an 84-pin plastic leaded chip carrier at commercial θjc, and the junction to ambient air characteristics is θja. The temperature is as follows: thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. Max junction te m p.(°C) – Max commercial te m p . ( ° C ) 150°C – 70°C -----------------------------θ--------------------------------------------- = ------------------ = 2.2 W ja(°C ⁄ W) 37°C ⁄ W θ
ja
θ
ja Package Type Pin Count
θ
jc Still Air 300 ft/min Units
44 15 45 35 °C/W Plastic J-Leaded Chip Carrier 68 13 38 29 °C/W 84 12 37 28 °C/W Plastic Quad Flatpack 100 13 48 40 °C/W Very Thin (1.0 mm) Quad Flatpack 80 12 43 35 °C/W Ceramic Pin Grid Array 84 8 33 20 °C/W Ceramic Quad Flatpack 84 5 40 30 °C/W
G e n e r a l P o w e r E q u a t i o n
The power due to standby current is typically a small P = [I component of the overall power. Standby power is calculated CCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * below for commercial, worst case conditions. (VCC – VOH) * M I Where: CC VCC Power 3 mA 5.25 V 15.75 mW (max) ICCstandby is the current flowing when no inputs or outputs are changing. 1 mA 5.25 V 5.25 mW (typ) I 0.75 mA 3.60 V 2.70 mW (max) CCactive is the current flowing due to CMOS switching. I 0.30 mA 3.30 V 0.99 mW (typ) OL, IOH are TTL sink/source currents. V
Active Power Component
OL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to Power dissipation in CMOS devices is usually dominated by VOL. the active (dynamic) power dissipation. This component is M equals the number of outputs driving TTL loads to frequency dependent, a function of the logic and the VOH. external I/O. Active power dissipation results from charging An accurate determination of N and M is problematical internal chip capacitances of the interconnect, because their values depend on the family type, design unprogrammed antifuses, module inputs, and module details, and on the system I/O. The power can be divided into outputs, plus external capacitance due to PC board traces two components: static and active. and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS
Static Power Component
transistor pairs. The net effect can be associated with an Actel FPGAs have small static power components that result equivalent capacitance that can be combined with frequency in lower power dissipation than PALs or PLDs. By integrating and voltage to represent active power dissipation. multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved.
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Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP