Datasheet ACT 1 (Actel) - 3

A C T ™ 1 S e r i e s F P G A s
source 10 mA at TTL levels. See Electrical Specifications for
A C T 1 A r r a y P e r f o r m a n c e
additional I/O buffer specifications.
Temperature and Voltage Effects D e v i c e O r g a n i z a t i o n
Worst-case delays for ACT 1 arrays are calculated in the same manner as for masked array products. A typical delay ACT 1 devices consist of a matrix of logic modules arranged in parameter is multiplied by a derating factor to account for rows separated by wiring channels. This array is surrounded temperature, voltage, and processing effects. However, in an by a ring of peripheral circuits including I/O buffers, ACT 1 array, temperature and voltage effects are less testability circuits, and diagnostic probe circuits providing dramatic than with masked devices. The electrical real-time diagnostic capability. Between rows of logic characteristics of module interconnections on ACT 1 devices modules are routing channels containing sets of segmented remain constant over voltage and temperature fluctuations. metal tracks with PLICE antifuses. Each channel has 22 signal tracks. Vertical routing is permitted via 13 vertical As a result, the total derating factor from typical to tracks per logic module column. The resulting network allows worst-case for a standard speed ACT 1 array is only 1.19 to 1, arbitrary and flexible interconnections between logic compared to 2 to 1 for a masked gate array. modules and I/O modules.
Logic Module Size
Logic module size also affects performance. A mask
P r o b e P i n
programmed gate array cell with four transistors usually ACT 1 devices have two independent diagnostic probe pins. implements only one logic level. In the more complex logic These pins allow the user to observe any two internal signals module (similar to the complexity of a gate array macro) of by entering the appropriate net name in the diagnostic an ACT 1 array, implementation of multiple logic levels software. Signals may be viewed on a logic analyzer using within a single module is possible. This eliminates interlevel Actel’s Actionprobe® diagnostic tools. The probe pins can wiring and associated RC delays. The effect is termed “net also be used as user-defined I/Os when debugging is finished. compression.”
O r d e r i n g I n f o r m a t i o n A1010 B – 2 PL 84 C
Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Package Type PL = Plastic J-Leaded Chip Carriers PQ = Plastic Quad Flatpacks CQ = Ceramic Quad Flatpack PG = Ceramic Pin Grid Array VQ = Very Thin Quad Flatpack Speed Grade Blank = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard Die Revision B = 1.0 micron CMOS Process Part Number A1010 = 1200 Gates (5 V) A1020 = 2000 Gates (5 V) A10V10 = 1200 Gates (3.3 V) A10V20 = 2000 Gates (3.3 V)
1-285
Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP