Datasheet STM32F103x8, STM32F103xB (STMicroelectronics) - 3

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STM32F103x8, STM32F103xB
5.1.1 Minimum and maximum values . 35 5.1.2 Typical values . 35 5.1.3 Typical curves . 35 5.1.4 Loading capacitor . 35 5.1.5 Pin input voltage . 35 5.1.6 Power supply scheme . 36 5.1.7 Current consumption measurement . 36 5.2 Absolute maximum ratings . 37 5.3 Operating conditions . 38 5.3.1 General operating conditions . 38 5.3.2 Operating conditions at power-up / power-down . 39 5.3.3 Embedded reset and power control block characteristics . 39 5.3.4 Embedded reference voltage . 40 5.3.5 Supply current characteristics . 40 5.3.6 External clock source characteristics . 50 5.3.7 Internal clock source characteristics . 54 5.3.8 PLL characteristics . 56 5.3.9 Memory characteristics . 56 5.3.10 EMC characteristics . 57 5.3.11 Absolute maximum ratings (electrical sensitivity) . 59 5.3.12 I/O current injection characteristics . 60 5.3.13 I/O port characteristics . 61 5.3.14 NRST pin characteristics . 66 5.3.15 TIM timer characteristics . 67 5.3.16 Communications interfaces . 68 5.3.17 CAN (controller area network) interface . 73 5.3.18 12-bit ADC characteristics . 74 5.3.19 Temperature sensor characteristics . 78
6 Package information . 79
6.1 Device marking . 79 6.2 VFQFPN36 package information . 80 6.3 UFQFPN48 package information (A0B9) . 83 6.4 LFBGA100 package information . 85 6.5 LQFP100 package information (1L) . 87 6.6 UFBGA100 package information (A0C2) . 90 DS5319 Rev 19 3/114 4 Document Outline Table 1. Device summary 1 Introduction 2 Description 2.1 Device overview Table 2. STM32F103xx medium-density device features and peripheral counts Figure 1. STM32F103xx performance line block diagram Figure 2. Clock tree 2.2 Full compatibility throughout the family Table 3. STM32F103xx family 2.3 Overview 2.3.1 Arm® Cortex®-M3 core with embedded flash and SRAM 2.3.2 Embedded flash memory 2.3.3 CRC (cyclic redundancy check) calculation unit 2.3.4 Embedded SRAM 2.3.5 Nested vectored interrupt controller (NVIC) 2.3.6 External interrupt/event controller (EXTI) 2.3.7 Clocks and startup 2.3.8 Boot modes 2.3.9 Power supply schemes 2.3.10 Power supply supervisor 2.3.11 Voltage regulator 2.3.12 Low-power modes 2.3.13 DMA 2.3.14 RTC (real-time clock) and backup registers 2.3.15 Timers and watchdogs Table 4. Timer feature comparison 2.3.16 I²C bus 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) 2.3.18 Serial peripheral interface (SPI) 2.3.19 Controller area network (CAN) 2.3.20 Universal serial bus (USB) 2.3.21 GPIOs (general-purpose inputs/outputs) 2.3.22 ADC (analog-to-digital converter) 2.3.23 Temperature sensor 2.3.24 Serial wire JTAG debug port (SWJ-DP) 3 Pinouts and pin description Figure 3. STM32F103xx performance line LFBGA100 ballout Figure 4. STM32F103xx performance line LQFP100 pinout Figure 5. STM32F103xx performance line UFBGA100 pinout Figure 6. STM32F103xx performance line LQFP64 pinout Figure 7. STM32F103xx performance line TFBGA64 ballout Figure 8. STM32F103xx performance line LQFP48 pinout Figure 9. STM32F103xx performance line UFQFPN48 pinout Figure 10. STM32F103xx performance line VFQFPN36 pinout Table 5. Medium-density STM32F103xx pin definitions 4 Memory mapping Figure 11. Memory map 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage Figure 12. Pin loading conditions Figure 13. Pin input voltage 5.1.6 Power supply scheme Figure 14. Power supply scheme 5.1.7 Current consumption measurement Figure 15. Current consumption measurement scheme 5.2 Absolute maximum ratings Table 6. Voltage characteristics Table 7. Current characteristics Table 8. Thermal characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 9. General operating conditions 5.3.2 Operating conditions at power-up / power-down Table 10. Operating conditions at power-up / power-down 5.3.3 Embedded reset and power control block characteristics Table 11. Embedded reset and power control block characteristics 5.3.4 Embedded reference voltage Table 12. Embedded internal reference voltage 5.3.5 Supply current characteristics Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Figure 16. Typical current consumption in Run mode versus frequency (at 3.6 V), code with data processing running from RAM, peripherals enabled Figure 17. Typical current consumption in Run mode versus frequency (at 3.6 V), code with data processing running from RAM, peripherals disabled Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Table 16. Typical and maximum current consumptions in Stop and Standby modes Figure 18. Typical current consumption on VBAT (RTC on) Figure 19. Typical current consumption in Stop mode, with regulator in Run mode Figure 20. Typical current consumption in Stop mode, with regulator in Low-power mode Figure 21. Typical current consumption in Standby mode Table 17. Typical current consumption in Run mode, code with data processing running from Flash Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Table 19. Peripheral current consumption 5.3.6 External clock source characteristics Table 20. High-speed external user clock characteristics Table 21. Low-speed external user clock characteristics Figure 22. High-speed external clock source AC timing diagram Figure 23. Low-speed external clock source AC timing diagram Table 22. HSE 4-16 MHz oscillator characteristics Figure 24. Typical application with an 8 MHz crystal Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 25. Typical application with a 32.768 kHz crystal 5.3.7 Internal clock source characteristics Table 24. HSI oscillator characteristics Table 25. LSI oscillator characteristics Table 26. Low-power mode wakeup timings 5.3.8 PLL characteristics Table 27. PLL characteristics 5.3.9 Memory characteristics Table 28. Flash memory characteristics Table 29. Flash memory endurance and data retention 5.3.10 EMC characteristics Table 30. EMS characteristics Table 31. EMI characteristics for fHSE = 8 MHz and fHCLK = 48 MHz Table 32. EMI characteristics for fHSE = 8 MHz and fHCLK = 72 MHz 5.3.11 Absolute maximum ratings (electrical sensitivity) Table 33. ESD absolute maximum ratings Table 34. Electrical sensitivities 5.3.12 I/O current injection characteristics Table 35. I/O current injection susceptibility 5.3.13 I/O port characteristics Table 36. I/O static characteristics Figure 26. Standard I/O input characteristics - CMOS port Figure 27. Standard I/O input characteristics - TTL port Figure 28. 5 V tolerant I/O input characteristics - CMOS port Figure 29. 5 V tolerant I/O input characteristics - TTL port Table 37. Output voltage characteristics Table 38. I/O AC characteristics Figure 30. I/O AC characteristics definition 5.3.14 NRST pin characteristics Table 39. NRST pin characteristics Figure 31. Recommended NRST pin protection 5.3.15 TIM timer characteristics Table 40. TIMx characteristics 5.3.16 Communications interfaces Table 41. I2C characteristics Figure 32. I2C bus AC waveforms and measurement circuit Table 42. SCL frequency (fPCLK1 = 36 MHz, VDD_I2C = 3.3 V) Table 43. SPI characteristics Figure 33. SPI timing diagram - slave mode and CPHA = 0 Figure 34. SPI timing diagram - slave mode and CPHA = 1 Figure 35. SPI timing diagram - master mode Table 44. USB startup time Table 45. USB DC electrical characteristics Figure 36. USB timings: definition of data signal rise and fall time Table 46. USB: Full-speed electrical characteristics 5.3.17 CAN (controller area network) interface 5.3.18 12-bit ADC characteristics Table 47. ADC characteristics Table 48. RAIN max for fADC = 14 MHz Table 49. ADC accuracy - Limited test conditions Table 50. ADC accuracy Figure 37. ADC accuracy characteristics Figure 38. Typical connection diagram using the ADC Figure 39. Power supply and reference decoupling (VREF+ not connected to VDDA) Figure 40. Power supply and reference decoupling (VREF+ connected to VDDA) 5.3.19 Temperature sensor characteristics Table 51. TS characteristics 6 Package information 6.1 Device marking 6.2 VFQFPN36 package information Figure 41. VFQFPN - 36 pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package outline Table 52. VFQFPN - 36 pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package mechanical data Figure 42. VFQFPN - 36 pin, 6x6 mm, 0.5 mm pitch very thin profile fine pitch quad flat package recommended footprint 6.3 UFQFPN48 package information (A0B9) Figure 43. UFQFPN48 – Outline Table 53. UFQFPN48 – Mechanical data Figure 44. UFQFPN48 – Footprint example 6.4 LFBGA100 package information Figure 45. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline Table 54. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data Figure 46. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package recommended footprint Table 55. LFBGA100 recommended PCB design rules (0.8 mm pitch BGA) 6.5 LQFP100 package information (1L) Figure 47. LQFP100 - Outline(15) Table 56. LQFP100 - Mechanical data Figure 48. LQFP100 - Footprint example 6.6 UFBGA100 package information (A0C2) Figure 49. UFBGA100 - Outline(13) Table 57. UFBGA100 - Mechanical data Figure 50. UFBGA100 - Footprint example Table 58. UFBGA100 - Example of PCB design rules (0.5 mm pitch BGA) 6.7 LQFP64 package information (5W) Figure 51. LQFP64 - Outline(15) Table 59. LQFP64 - Mechanical data Figure 52. LQFP64 - Footprint example 6.8 TFBGA64 package information Figure 53. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline Table 60. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data Figure 54. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array , recommended footprint Table 61. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA) 6.9 LQFP48 package information (5B) Figure 55. LQFP48 – Outline(15) Table 62. LQFP48 – Mechanical data Figure 56. LQFP48 – Footprint example 6.10 Thermal characteristics Table 63. Package thermal characteristics 6.10.1 Reference document 6.10.2 Selecting the product temperature range Figure 57. LQFP100 PD max vs. TA 7 Ordering information scheme 8 Important security notice 9 Revision history Table 64. Document revision history