Datasheet FL7740 (ON Semiconductor) - 5
| Fabricante | ON Semiconductor |
| Descripción | PWM Controller, Constant Voltage, Primary Side Regulation for Power Factor Correction |
| Páginas / Página | 15 / 5 — FL7740. ELECTRICAL CHARACTERISTICS. Symbol. Parameter. Test Conditions. … |
| Formato / tamaño de archivo | PDF / 422 Kb |
| Idioma del documento | Inglés |
FL7740. ELECTRICAL CHARACTERISTICS. Symbol. Parameter. Test Conditions. Min. Typ. Max. Unit. HW Section. PWM Section. Oscillator Section
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FL7740 ELECTRICAL CHARACTERISTICS
(continued) VDD = 18 V and TJ = −40 ~ 125°C unless otherwise specified
Symbol Parameter Test Conditions Min Typ Max Unit HW Section
IHV−LC Leakage Current after Startup 1 10 A tR−JFET JFET Regulation Time at Startup Design guaranteed 400 500 600 ms VDD−JFET−HL VDD High Limit during JFET Regulation 17.5 19.0 20.5 V VDD−JFET−LL VDD Low Limit during JFET Regulation 15.5 17.0 18.5 V
PWM Section
TON−MIN−MIN Min. Turn−on Time Min. Limit Design guaranteed 0.40 s TON−MIN−MAX Min. Turn−on Time Max. Limit Design guaranteed 2.0 s TON−MAX Max. Turn−on Time Design guaranteed 23.3 s
Oscillator Section
fMAX Max. Frequency 60 65 70 kHz fMIN Min. Frequency 0.72 0.80 0.88 kHz
Current Sense Section
tLEB Leading−Edge Blanking Time Design guaranteed 300 ns tPD Propagation Delay to GATE Design guaranteed 50 100 150 ns
Voltage Sense Section
tDIS−BNK tDIS Blanking Time at VS Sampling Design guaranteed 0.95 1.00 1.05 s VVS−CLAMP VS Clamping Voltage IVS=1 mA −0.1 0.35 V IVS=10 A VREF Reference Voltage 3.465 3.5 3.535 V CVREGULATION CV Regulation Tolerance VVS = 3.5 V, TJ = 25°C −0.7 +0.7 % VVS = 3.5 V, TJ = −40~125°C −1.2 +1.2 gM Transconductance 16 20 24 mho ICOMV−SINK COMV Sink Current VVS = 4 V 8 10 12 A ICOMV−SOURCE COMV Source Current VVS = 3 V 8 10 12 A VCOMV−HGH COMV High Voltage 4.7 V VCOMV−LOW COMV Low Voltage 0.1 V
Start Sequence Section
tSOFT−START Soft Start Time Design guaranteed 25.6 ms tSS1−MIN SS1 Minimum Time Design guaranteed 2 ms tSS1−MAX SS1 Maximum Time Design guaranteed 100 ms tSS21 SS21 Time Design guaranteed 45 ms tSS22 SS22 Maximum Time Design guaranteed 30 ms
Dynamic Section
VDYN−REF−SET DYN Reference Set Threshold 0.72 0.80 0.88 V tDYN−REF−SET DYN Reference Set Time Design guaranteed 5 s VOV−REF5 OV Reference 5 Design guaranteed +20 % VOV−REF4 OV Reference 4 +14 +15 +16 % VOV−REF3 OV Reference 3 +9 +10 +11 % VOV−REF2 OV Reference 2 +4.7 +5.7 +6.7 % VOV−REF1 OV Reference 1 +1.86 +2.86 +3.86 % VUV−REF1 UV Reference 1 −3.86 −2.86 −1.86 % VUV−REF2 UV Reference 2 −6.7 −5.7 −4.7 % VUV−REF3 UV Reference 3 Design guaranteed −10 %
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(continued) VDD = 18 V and TJ = −40 ~ 125°C unless otherwise specified
Symbol Parameter Test Conditions Min Typ Max Unit HW Section
IHV−LC Leakage Current after Startup 1 10 A tR−JFET JFET Regulation Time at Startup Design guaranteed 400 500 600 ms VDD−JFET−HL VDD High Limit during JFET Regulation 17.5 19.0 20.5 V VDD−JFET−LL VDD Low Limit during JFET Regulation 15.5 17.0 18.5 V
PWM Section
TON−MIN−MIN Min. Turn−on Time Min. Limit Design guaranteed 0.40 s TON−MIN−MAX Min. Turn−on Time Max. Limit Design guaranteed 2.0 s TON−MAX Max. Turn−on Time Design guaranteed 23.3 s
Oscillator Section
fMAX Max. Frequency 60 65 70 kHz fMIN Min. Frequency 0.72 0.80 0.88 kHz
Current Sense Section
tLEB Leading−Edge Blanking Time Design guaranteed 300 ns tPD Propagation Delay to GATE Design guaranteed 50 100 150 ns
Voltage Sense Section
tDIS−BNK tDIS Blanking Time at VS Sampling Design guaranteed 0.95 1.00 1.05 s VVS−CLAMP VS Clamping Voltage IVS=1 mA −0.1 0.35 V IVS=10 A VREF Reference Voltage 3.465 3.5 3.535 V CVREGULATION CV Regulation Tolerance VVS = 3.5 V, TJ = 25°C −0.7 +0.7 % VVS = 3.5 V, TJ = −40~125°C −1.2 +1.2 gM Transconductance 16 20 24 mho ICOMV−SINK COMV Sink Current VVS = 4 V 8 10 12 A ICOMV−SOURCE COMV Source Current VVS = 3 V 8 10 12 A VCOMV−HGH COMV High Voltage 4.7 V VCOMV−LOW COMV Low Voltage 0.1 V
Start Sequence Section
tSOFT−START Soft Start Time Design guaranteed 25.6 ms tSS1−MIN SS1 Minimum Time Design guaranteed 2 ms tSS1−MAX SS1 Maximum Time Design guaranteed 100 ms tSS21 SS21 Time Design guaranteed 45 ms tSS22 SS22 Maximum Time Design guaranteed 30 ms
Dynamic Section
VDYN−REF−SET DYN Reference Set Threshold 0.72 0.80 0.88 V tDYN−REF−SET DYN Reference Set Time Design guaranteed 5 s VOV−REF5 OV Reference 5 Design guaranteed +20 % VOV−REF4 OV Reference 4 +14 +15 +16 % VOV−REF3 OV Reference 3 +9 +10 +11 % VOV−REF2 OV Reference 2 +4.7 +5.7 +6.7 % VOV−REF1 OV Reference 1 +1.86 +2.86 +3.86 % VUV−REF1 UV Reference 1 −3.86 −2.86 −1.86 % VUV−REF2 UV Reference 2 −6.7 −5.7 −4.7 % VUV−REF3 UV Reference 3 Design guaranteed −10 %
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