Datasheet SA571 (ON Semiconductor) - 4

SA571 Circuit Description
as brought out externally. A resistor, R3, is brought out from The SA571 compandor building blocks, as shown in the the summing node and allows compressor or expander gain block diagram, are a full−wave rectifier, a variable gain cell, to be determined only by internal components. an operational amplifier and a bias system. The arrangement The output stage is capable of ± 20 mA output current. of these blocks in the IC result in a circuit which can perform This allows a +13 dBm (3.5 VRMS) output into a 300 W load well with few external components, yet can be adapted to which, with a series resistor and proper transformer, can many diverse applications. result in +13 dBm with a 600 W output impedance. The full−wave rectifier rectifies the input current which A bandgap reference provides the reference voltage for all flows from the rectifier input, to an internal summing node summing nodes, a regulated supply voltage for the rectifier which is biased at VREF. The rectified current is averaged on and DG cell, and a bias current for the DG cell. The low an external filter capacitor tied to the CRECT terminal, and tempco of this type of reference provides very stable biasing the average value of the input current controls the gain of the over a wide temperature range. variable gain cell. The gain will thus be proportional to the The typical performance characteristics illustration average value of the input signal for capacitively−coupled shows the basic input−output transfer curve for basic voltage inputs as shown in the following equation. Note that compressor or expander circuits. for capacitively−coupled inputs there is no offset voltage capable of producing a gain error. The only error will come +20 from the bias current of the rectifier (supplied internally) +10 which is less than 0.1 mA. ANDOR 0 |V * V | avg G T IN REF −10 R1 or OR EXP −20 (dBm) | V | avg −30 G T IN LEVEL R LEVEL 1 −40 The speed with which gain changes to follow changes in −50 input signal levels is determined by the rectifier filter OUTPUT −60 capacitor. A small capacitor will yield rapid response but −70 will not fully filter low frequency signals. Any ripple on the gain control signal will modulate the signal passing through −80 COMPRESSOR INPUT the variable gain cell. In an expander or compressor −40 −30 −20 −10 0 +10 application, this would lead to third harmonic distortion, so COMPRESSOR OUTPUT LEVEL there is a trade−off to be made between fast attack and decay OR times and distortion. For step changes in amplitude, the EXPANDOR INPUT LEVEL (dBm) change in gain with time is shown by this equation.
Figure 2. Basic Input−Output Transfer Curve
*t G(t) + (G * G ) e t ) G initial final final t + 10kW C VCC = 15V RECT 0.1 10 mF mF The variable gain cell is a current−in, current−out device with the ratio I 13 OUT/IIN controlled by the rectifier. IIN is the 6, 11 current which flows from the DG input to an internal summing node biased at VREF. The following equation 20kW applies for capacitively−coupled inputs. The output current, 2.2mF 20kW V DG − I 1 OUT, is fed to the summing node of the op amp. VO 3, 14 + 7, 10 V * V V I + IN REF + IN IN R R V 2 2 REF 2.2mF A compensation scheme built into the DG cell 10kW V2 compensates for temperature and cancels out odd harmonic 2, 15 30kW distortion. The only distortion which remains is even harmonics, and they exist only because of internal offset 4 1, 16 5, 12 8, 9 voltages. The THD trim terminal provides a means for 200pF nulling the internal offsets for low distortion operation. 2.2mF 8.2kW The operational amplifier (which is internally compensated) has the non−inverting input tied to VREF, and
Figure 3. Typical Test Circuit
the inverting input connected to the DG cell output as well
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