Datasheet TH7122 (Melexis) - 5

TH7122 27 to 930MHz FSK/FM/ASK Transceiver 1.4 Block Diagram
27
A
29
A
28
A
30
IX
32
IX
31
_IF
1 2
IF
7 3
IN_DEM
6
OUT_DEM LN SSI _LN LN _M _IFA R IN T_ T_M IN U IN VEE VCC_ PKDET VEE_ GA O OU SW1 bias
4
OA2 INT2/PDO FSK Demodulator
1.5pF 5
IN_LNA MIX MIX INT1 LNA IFA
26
IF SW2
8
OA1 OUT_DTA LO
200k
Control Logic SCI N R
SDE SDT SCL
counter counter ASK
N A K
VCO RO RO FSK OUT_PA PA
25
K O EN IG IG R TA TA _SW D /SD K 1/LD E_ _D K/FSK /SCL /SD E_ C_D
24
PS_PA
21
TNK_LO
20
VCC_PLL
23
LF
22
VEE_PLL
10
RO
11
FS
19
FS
9
VE
12
IN
13
AS
15
RE
16
TE
17
FS0
18
VE
14
VC
Fig. 1: TH7122 block diagram
1.5 User Mode Features
The transceiver can operate in two different user modes. It can be used either as a 3wire-bus-controlled programmable or as a stand-alone fixed-frequency device. After power up, the transceiver is set to Stand- alone User Mode (SUM). In this mode, pins FS0/SDEN and FS1/LD must be connected to VEE or VCC in order to set the desired frequency of operation. There are 4 pre-defined frequency settings: 315MHz, 433.92MHz, 868.3MHz and 915MHz. The logic level at pin FS0/SDEN must not be changed after power up in order to remain in fixed-frequency mode. After the first logic level change at pin FS0/SDEN, the transceiver enters into Programmable User Mode (PUM). In this mode, the user can set any PLL frequency or mode of operation by the SCI. In SUM pins FS0/SDEN and FS1/LD are used to set the desired frequency, while in PUM pin FS0/SDEN is part of the 3-wire serial control interface (SCI) and pin FS1/LD is the look detector output signal of the PLL synthesizer. A mode control logic allows several operating modes. In addition to standby, transmit and receive mode, two idle modes can be selected to run either the reference oscillator only or the whole PLL synthesizer. The PLL settings for the PLL idle mode are taken over from the last operating mode which can be either receive or transmit mode. The different operating modes can be set in SUM and PUM as well. In SUM the user can program the trans- ceiver via control pins RE/SCLK and TE/SDTA. In PUM the register bits OPMODE are used to select the modes of operation while pins RE/SCLK and TE/SDTA are part of the SCI. 39010 07122 Page 5 of 44 Data Sheet Rev. 008 June/07 Document Outline Features Ordering Information Application Examples Pin Description General Description Document Content 1 Theory of Operation 1.1 General 1.2 Technical Data Overview 1.3 Note on ASK Operation 1.4 Block Diagram 1.5 User Mode Features 2 Pin Definitions and Descriptions 3 Functional Description 3.1 PLL Frequency Synthesizer 3.1.1 Reference Oscillator (XOSC) 3.1.2 Reference Divider 3.1.3 Feedback Divider 3.1.4 Frequency Resolution and Operating Frequency 3.1.5 Phase-Frequency Detector 3.1.6 Lock Detector 3.1.7 Voltage Controlled Oscillator with external Loop Filter 3.1.8 Loop Filter Receiver Part 3.2.1 LNA 3.2.2 Mixer 3.2.3 IF Amplifier 3.2.4 ASK Demodulator 3.2.5 FSK Demodulator 3.3 Transmitter Part 3.3.1 Power Amplifier Output Power Adjustment 3.3.3 Modulation Schemes 3.3.4 ASK Modulation 3.3.5 FSK Modulation 3.3.6 Crystal Tuning 4 Description of User Modes 4.1 Stand-alone User Mode Operation 4.1.1 Frequency Selection 4.1.2 Operation Mode 4.1.3 Modulation Type 4.1.4 LNA Gain Mode 4.2 Programmable User Mode Operation 4.2.1 Serial Control Interface Description 5 Register Description 5.1 Register Overview 5.1.1 Default Register Settings for FS0, FS1 5.1.2 A – word 5.1.3 B – word 5.1.4 C – word 5.1.5 D – word 6 Technical Data 6.1 Absolute Maximum Ratings 6.2 Normal Operating Conditions 6.3 DC Characteristics 6.4 PLL Synthesizer Timings 6.5 AC Characteristics of the Receiver Part 6.6 AC Characteristics of the Transmitter Part 6.7 Serial Control Interface 6.8 Crystal Parameters 7 Application Circuit Examples 7.1 FSK Application Circuit Programmable User Mode (internal AFC option) 7.2 FSK Application Circuit Stand-alone User Mode 7.3 FSK Test Circuit Component List (Fig. 14 and Fig. 15) 7.4 ASK Application Circuit Programmable User Mode (normal data slicer option) 7.5 ASK Test Circuit Component List (Fig. 16) 7.6 ASK Application Circuit Programmable User Mode (peak detector option) 7.7 ASK Test Circuit Component List (Fig. 17) 8 Extended Frequency Range 8.1 Board Component List (Fig. 18) 9 TX/RX Combining Network 9.1 Board Component List (Fig. 19) 9.2 Typical LNA S-Parameters in Receive Mode 9.3 LNA Input Impedances in Transmit Mode 10 Package Description 10.1 Soldering Information 11 Reliability Information 12 ESD Precautions Your Notes 13 Disclaimer