Datasheet DG20001E (Vishay) - 8
| Fabricante | Vishay |
| Descripción | Powered-off Protection, 0.85 , 1.8 V to 5.5 V, SPDT Analog Switch (2:1 Multiplexer) |
| Páginas / Página | 12 / 8 — DG2001E. TEST CIRCUITS. Fig. 1 - Switching Time. Fig. 2 - … |
| Formato / tamaño de archivo | PDF / 217 Kb |
| Idioma del documento | Inglés |
DG2001E. TEST CIRCUITS. Fig. 1 - Switching Time. Fig. 2 - Break-Before-Make Interval. Fig. 3 - Charge Injection
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DG2001E
www.vishay.com Vishay Siliconix
TEST CIRCUITS
V+ + 3 V Logic tr < 20 ns 50 % Input tf < 20 ns V+ 0 V Switch Output Switch NO or NC COM Input VOUT 0.9 x VOUT IN Switch R C Output L L 300 Ω 35 pF Logic GND 0 V Input tON tOFF 0 V Logic "1" = Switch On CL (includes fixture and stray capacitance) Logic input waveforms inverted for switches that have the opposite logic sense. R V = V L OUT COM R + R L ON
Fig. 1 - Switching Time
V+ Logic 3 V tr < 5 ns Input tf < 5 ns V+ NO COM 0 V VNO VO NC VNC R C L L V 300 Ω 35 pF NC = VNO IN VO 90 % GND Switch 0 V Output tD tD CL (includes fixture and stray capacitance)
Fig. 2 - Break-Before-Make Interval
V+ V+ ΔVOUT Rgen V NC or NO COM OUT VOUT + IN V IN gen CL On On Off 3 V GND Q = ΔVOUT x CL IN depends on switch configuration: input polarity determined by sense of switch.
Fig. 3 - Charge Injection
S18-0426-Rev. B, 23-Apr-18
8
Document Number: 76471 For technical questions, contact: analogswitchtechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
TEST CIRCUITS
V+ + 3 V Logic tr < 20 ns 50 % Input tf < 20 ns V+ 0 V Switch Output Switch NO or NC COM Input VOUT 0.9 x VOUT IN Switch R C Output L L 300 Ω 35 pF Logic GND 0 V Input tON tOFF 0 V Logic "1" = Switch On CL (includes fixture and stray capacitance) Logic input waveforms inverted for switches that have the opposite logic sense. R V = V L OUT COM R + R L ON
Fig. 1 - Switching Time
V+ Logic 3 V tr < 5 ns Input tf < 5 ns V+ NO COM 0 V VNO VO NC VNC R C L L V 300 Ω 35 pF NC = VNO IN VO 90 % GND Switch 0 V Output tD tD CL (includes fixture and stray capacitance)
Fig. 2 - Break-Before-Make Interval
V+ V+ ΔVOUT Rgen V NC or NO COM OUT VOUT + IN V IN gen CL On On Off 3 V GND Q = ΔVOUT x CL IN depends on switch configuration: input polarity determined by sense of switch.
Fig. 3 - Charge Injection
S18-0426-Rev. B, 23-Apr-18
8
Document Number: 76471 For technical questions, contact: analogswitchtechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000