Datasheet SY58608U (Microchip) - 6
| Fabricante | Microchip |
| Descripción | 2.5V, high-speed, fully differential 1:2 LVDS fanout buffer optimized to provide two identical output copies with less than 20ps of skew and less than 10psPP total jitter |
| Páginas / Página | 24 / 6 — SY58608U. 2.0. FUNCTIONAL DESCRIPTION. 2.1. Fail-Safe Input (FSI). 2.2. … |
| Formato / tamaño de archivo | PDF / 2.7 Mb |
| Idioma del documento | Inglés |
SY58608U. 2.0. FUNCTIONAL DESCRIPTION. 2.1. Fail-Safe Input (FSI). 2.2. Input Clock Failure Case
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SY58608U 2.0 FUNCTIONAL DESCRIPTION 2.1 Fail-Safe Input (FSI) 2.2 Input Clock Failure Case
The input includes a special fail-safe circuit to sense If the input clock fails to a floating, static, or extremely the amplitude of the input signal and to latch the low signal swing such that the differential voltage outputs when there is no input signal present, or when across the input pair is less than 100 mV, the FSI the amplitude of the input signal drops sufficiently function will eliminate a metastable condition and latch below 100 mVPK (200 mVPP), typically 30 mVPK. the outputs to the last valid state. No ringing and no Maximum frequency of SY58608U is limited by the FSI indeterminate state will occur at the output under these function. conditions. The output recovers to normal operation once the input signal returns to a valid state with a differential voltage ≥100 mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but stil toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Performance Curves” for detailed information. DS20005605A-page 6 2018 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 2.0 Functional Description 2.1 Fail-Safe Input (FSI) 2.2 Input Clock Failure Case 3.0 Timing Diagrams 4.0 Typical Performance Curves 5.0 Additive Phase Noise Plot 6.0 Input Stage 7.0 Input Interface Applications 8.0 Pin Descriptions 9.0 Packaging Information 9.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service
SY58608U 2.0 FUNCTIONAL DESCRIPTION 2.1 Fail-Safe Input (FSI) 2.2 Input Clock Failure Case
The input includes a special fail-safe circuit to sense If the input clock fails to a floating, static, or extremely the amplitude of the input signal and to latch the low signal swing such that the differential voltage outputs when there is no input signal present, or when across the input pair is less than 100 mV, the FSI the amplitude of the input signal drops sufficiently function will eliminate a metastable condition and latch below 100 mVPK (200 mVPP), typically 30 mVPK. the outputs to the last valid state. No ringing and no Maximum frequency of SY58608U is limited by the FSI indeterminate state will occur at the output under these function. conditions. The output recovers to normal operation once the input signal returns to a valid state with a differential voltage ≥100 mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but stil toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to “Typical Performance Curves” for detailed information. DS20005605A-page 6 2018 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 2.0 Functional Description 2.1 Fail-Safe Input (FSI) 2.2 Input Clock Failure Case 3.0 Timing Diagrams 4.0 Typical Performance Curves 5.0 Additive Phase Noise Plot 6.0 Input Stage 7.0 Input Interface Applications 8.0 Pin Descriptions 9.0 Packaging Information 9.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service