link to page 8 link to page 8 link to page 7 link to page 8 link to page 9 link to page 8 link to page 9 link to page 8 link to page 9 NCP51460APPLICATIONS INFORMATIONInput Decoupling Capacitor (CIN) It is recommended to connect a 0.1 mF Ceramic capacitor between V C IN and GND pin of the device. This capacitor will 3.35 V OUT = 1 mF MLCC + 2 W OUT provide a low impedance path for unwanted AC signals or 3.30 noise present on the input voltage. The input capacitor will 3.25 also limit the influence of input trace inductances and Power Supply resistance during sudden load current changes. TAGE (50 mV/DIV) 3.35 COUT = 1 mF MLCC Higher capacitances will improve the Power Supply 3.30 Rejection Ratio and line transient response. 3.25 Output Decoupling Capacitor (C IOUT = 10 mA OUT) , OUTPUT VOL V The NCP51460 was designed to be stable without an IN = 5.8 V, TA = 25°C, trise_fall = 10 mA/1 ms additional output capacitor. Without the output capacitor the V OUT VOUT settling times during Reference Turn−on or Turn−off IOUT = 0 mA can be as short as 20 ms (Refer to Figure 24 and 25). The TIME (50 ms/DIV) Load Transient Responses without COUT (Figure 21 and 22) Figure 27. show good stability of NCP51460 even for fast output The device was determined to be stable with Aluminum, current changes from 0 mA to full load. If smaller VOUT Ceramic and Tantalum Capacitors with capacitances deviations during load current changes are required, it is ranging from 0 to 100 possible to add some external capacitance as shown on mF at TA = 25°C. Figure 26. Turn−On Response It is possible to achieve very fast Turn−On time when fast VIN = 4.2 to 28 V V VOUT IN VOUT VIN ramp is applied to NCP51460 input as shown on NCP51460 3.3 V Figure 24. However if the Input Voltage change from 0 V to CIN (3.3 V fixed) 0.1 mF GND C nominal Input Voltage is extremely fast, the Output Voltage OUT settling time will increase. Figure 28 below shows this effect when the Input Voltage change is 5.8 V / 2 ms. Figure 26. Output Capacitor Connection The C TAGE 6 OUT will reduce the overshoot and undershoot but will increase the settling time and can introduce some 4 ringing of the output voltage during fast load transients. 2 (2 V/DIV) VIN NCP51460 behavior for different values of ceramic X7R 0 , INPUT VOL output capacitors is depicted on Figure 23. V IN The Output Voltage ringing and settling times can be T- reduced by using some additional resistance in series with 3 the Ceramic Capacitor or by using Tantalum or Aluminum VIN = 0 V to 5.8 V, 2 C Capacitors which have higher ESR values. Figure 27 below IN = 0 mF, COUT = 0 mF, shows the Load Transient improvement after adding an 1 VOUT IOUT = 0 mA, TA = 25°C, additional 2 W series resistor to a 1 mF Ceramics Capacitor. , OUTPUT VOL 0 AGE (1 V/DIV) trise = 45 ms V OUT TIME (10 ms/DIV) Figure 28.www.onsemi.com8