Datasheet TLV431ASNT1G (ON Semiconductor) - 9
| Fabricante | ON Semiconductor |
| Descripción | Low Voltage Precision Adjustable Shunt Regulator |
| Páginas / Página | 19 / 9 — TLV431, NCV431, SCV431. Figure 16. Spectral Noise Density. Figure 17. … |
| Formato / tamaño de archivo | PDF / 402 Kb |
| Idioma del documento | Inglés |
TLV431, NCV431, SCV431. Figure 16. Spectral Noise Density. Figure 17. Pulse Response. Unstable. VKA. Regions. (V). (kW)
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TLV431, NCV431, SCV431
350 Input 1.8 kW Output Input Output IK Iref Hz) 325 1.5 VKA = Vref Pulse √ 50 IK = 10 mA Generator f = 100 kHz Output T 1.0 A = 25°C TS) TA = 25°C 300 0.5 TAGE (nV/ Input (VOL 0 275 NOISE VOL 2.0 0 250 10 100 1.0 k 10 k 100 k 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 f, FREQUENCY (Hz) t, TIME (ms)
Figure 16. Spectral Noise Density Figure 17. Pulse Response
25 1.0 k TA = 25°C IK R1 20 A Stable (mA) V+ CL 15 C R2 B Stable 10 THODE CURRENT , CA I K 5.0 Stable
Unstable VKA R1 R2 Regions (V) (kW) (kW)
D 010 100 1.0 0.01 0.1 1.0 10 100 A, C Vref 0 ∞ pF pF nF mF mF mF mF mF B, D 5.0 30.4 10 CL, LOAD CAPACITANCE
Figure 18. Stability Boundary Conditions Figure 19. Test Circuit for Figure 18 Stability
Figures 18 and 19 show the stability boundaries and equivalent series resistance (ESR). Ceramic or tantalum circuit configurations for the worst case conditions with the surface mount capacitors are recommended for both load capacitance mounted as close as possible to the device. temperature and ESR. The application circuit stability The required load capacitance for stable operation can vary should be verified over the anticipated operating current and depending on the operating temperature and capacitor temperature ranges.
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TLV431, NCV431, SCV431
350 Input 1.8 kW Output Input Output IK Iref Hz) 325 1.5 VKA = Vref Pulse √ 50 IK = 10 mA Generator f = 100 kHz Output T 1.0 A = 25°C TS) TA = 25°C 300 0.5 TAGE (nV/ Input (VOL 0 275 NOISE VOL 2.0 0 250 10 100 1.0 k 10 k 100 k 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 f, FREQUENCY (Hz) t, TIME (ms)
Figure 16. Spectral Noise Density Figure 17. Pulse Response
25 1.0 k TA = 25°C IK R1 20 A Stable (mA) V+ CL 15 C R2 B Stable 10 THODE CURRENT , CA I K 5.0 Stable
Unstable VKA R1 R2 Regions (V) (kW) (kW)
D 010 100 1.0 0.01 0.1 1.0 10 100 A, C Vref 0 ∞ pF pF nF mF mF mF mF mF B, D 5.0 30.4 10 CL, LOAD CAPACITANCE
Figure 18. Stability Boundary Conditions Figure 19. Test Circuit for Figure 18 Stability
Figures 18 and 19 show the stability boundaries and equivalent series resistance (ESR). Ceramic or tantalum circuit configurations for the worst case conditions with the surface mount capacitors are recommended for both load capacitance mounted as close as possible to the device. temperature and ESR. The application circuit stability The required load capacitance for stable operation can vary should be verified over the anticipated operating current and depending on the operating temperature and capacitor temperature ranges.
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