Datasheet FAN7318A (Fairchild) - 2

FA N 7318A Block Diagram — LC Short-Lamp Protection
Min.
D
-
50µA @ OVP,SLP B 0.3V
+
2µA @ OLP.CMP high
TIMER
a 3V/1V @ striking/normal cklight
OLR1
Over-Voltage Protection Protection Min. &
Max.
Max.
+
Detector
TSD 150oC
Invert /Full Wave 1.34V
-
Recifier
OLR2 +
e 2V r D
- OUTA
r 0μA ive IC Output Driver
+
3μA 1.34V
OUTB - Error. Amp. source current change -
Gm Amp. 2.2V
+
Open-Lamp Regulation
max. 2V
Oscillator
On @ striking
Control
min. 0.5V
Logic
CT - GND CMP + Error. Amp. source current change -
UVLO 5.5V
Negative
Error Amp. V
ADIM Analog
ref
+ + VIN Dimming + Hys. 0.45V High_CMP -
3.5V
- -
1.35V High CMP Protection
+ 52μA burst disable @ striking ENA sink current on 200k OLP max.
Striking off Voltage Reference 5V, max. 3mA
REF
& Internal Bias 17 Pulses Counter
OLP1
And OLR<1.4V Min. & Max. Detector
max. 2V
/Full or Half OLP Wave
OLP2
Rectifier
- min. 0.5V OLP min. BCT -
150μs
52μA burst
Delay
disable @ striking 0.7V/0.5V + sink current on + Striking/normal BDIM
If ENA>2.5V, OLP & SLP disable. If ENA<2.1V, OLP & SLP enable. Figure 1. Internal Block Diagram
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7318A • 1.0.0 2