Datasheet AL58221 (Diodes) - 5

AL58221 Electrical Characteristics
(VDD=5.0V @TA = +25°C, unless otherwise specified.)
CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT
Input Voltage “H” Level VIH CMOS logic level 0.7VDD ⎯ VDD V Input Voltage “L” Level VIL CMOS logic level GND ⎯ 0.3VDD Output Leakage Current ILK VOUT = 24 V ⎯ ⎯ 0.2 uA IOL VOL = 0.4V 3.5 4.6 8 Driving Current (DO) mA IOH VOH= VDD-0.4 -8 -4.6 -3 Output Current Skew (Channel-to-Channel) (Note 9) dIOUT1 VOUT = 1.0 V ⎯ 1 3 % Rrext = 2340 Output Current Skew (Chip-to-Chip) (Note 10) dIOUT2 ⎯ 2 6 % Rrext = 2340 Output Voltage Regulation (Note 11) % / VOUT ⎯ .0.1 ⎯ VOUT = 1 V ~ 3 V % / V Rrext = 2340 Supply Voltage Regulation (Note 12) % / VDD ⎯ 0.6 1 VDD = 3 V ~ 5.5 V Rrext = 2340 I ⎯ DD1(off) 5.73 ⎯ all outputs turn off Rrext = 2340 IDD2(on) 2.93 5.85 11.5 all outputs turn on Supply Current (Note 13) mA Rrext = 19.5 K I ⎯ DD3(off) 2.84 ⎯ all outputs turn off Rrext = 19.5 K IDD4(on) 1.42 2.84 8 all outputs turn on Notes: 9. Channel-to-channel skew is defined by the formula below: ( Iout %) =  n −1  100 * % (Iout + Iout + ...+ Iout ) 0 1 3 4 10. Chip-to-Chip skew is defined by the formula below: (Iout + Iout + ...+ Iout ) 0 1 3 − (Ideal Output Curren )t ( %) =  4 ( *10 % 0 (Ideal Output Curren ) t 11. Output voltage regulation is defined by the formula below: ( (@ = 3 ) − (@ =1 ) % 100 % /V ) =  Iout Vout V Iout Vout V n n n n * Iout (@Vout = V 3 ) V 3 − V 1 n n 12. Supply voltage regulation is defined by the formula below: ( (@ = 5 . 5 ) − (@ = 3 ) 100% % /V ) =  Iout V V Iout V V n DD n DD * Iout (@Vcc = V 3 ) V 5 . 5 − V 3 n 13. IO excluded. AL58221 5 of 26 April 2024 Document number: DS46476 Rev. 2 - 2
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