Datasheet TLV9101, TLV9102, TLV9104 (Texas Instruments) - 4
| Fabricante | Texas Instruments |
| Descripción | 16-V, 1-MHz, Rail-to-Rail Input/Output, Low Power Op Amp |
| Páginas / Página | 84 / 4 — TLV9101, TL. V9102,. TLV9104. www.ti.com. 5 Pin Configuration and … |
| Formato / tamaño de archivo | PDF / 6.9 Mb |
| Idioma del documento | Inglés |
TLV9101, TL. V9102,. TLV9104. www.ti.com. 5 Pin Configuration and Functions. Figure 5-1. TLV9101 DBV Package. 5-Pin SOT-23
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TLV9101, TL V9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com 5 Pin Configuration and Functions
OUT 1 5 V+ IN+ 1 5 V+ V 2 ± V 2 ± IN+ 3 4 IN± IN 3 ± 4 OUT Not to scale Not to scale
Figure 5-1. TLV9101 DBV Package
A. Package is preview only.
5-Pin SOT-23 Figure 5-2. TLV9101 DCK and DRL Package(A) Top View 5-Pin SC70 and SOT-553 Top View Table 5-1. Pin Functions: TLV9101 PIN I/O DESCRIPTION NAME DBV DCK and DRL
+IN 3 1 I Noninverting input –IN 4 3 I Inverting input OUT 1 4 O Output V+ 5 5 — Positive (highest) power supply V– 2 2 — Negative (lowest) power supply OUT 1 6 V+ V– 2 5 SHDN +IN 3 4 –IN Not to scale
Figure 5-3. TLV9101S DBV Package 6-Pin SOT-23 Top View Table 5-2. Pin Functions: TLV9101S PIN I/O DESCRIPTION NAME NO.
IN+ 3 I Noninverting input IN– 4 I Inverting input OUT 1 O Output Shutdown: low = amplifier enabled, high = amplifier disabled. See Section SHDN 5 I 7.3.10 for more information. V+ 6 — Positive (highest) power supply V– 2 — Negative (lowest) power supply 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information
TLV9101, TL V9102, TLV9104
SBOS943E – FEBRUARY 2019 – REVISED AUGUST 2021
www.ti.com 5 Pin Configuration and Functions
OUT 1 5 V+ IN+ 1 5 V+ V 2 ± V 2 ± IN+ 3 4 IN± IN 3 ± 4 OUT Not to scale Not to scale
Figure 5-1. TLV9101 DBV Package
A. Package is preview only.
5-Pin SOT-23 Figure 5-2. TLV9101 DCK and DRL Package(A) Top View 5-Pin SC70 and SOT-553 Top View Table 5-1. Pin Functions: TLV9101 PIN I/O DESCRIPTION NAME DBV DCK and DRL
+IN 3 1 I Noninverting input –IN 4 3 I Inverting input OUT 1 4 O Output V+ 5 5 — Positive (highest) power supply V– 2 2 — Negative (lowest) power supply OUT 1 6 V+ V– 2 5 SHDN +IN 3 4 –IN Not to scale
Figure 5-3. TLV9101S DBV Package 6-Pin SOT-23 Top View Table 5-2. Pin Functions: TLV9101S PIN I/O DESCRIPTION NAME NO.
IN+ 3 I Noninverting input IN– 4 I Inverting input OUT 1 O Output Shutdown: low = amplifier enabled, high = amplifier disabled. See Section SHDN 5 I 7.3.10 for more information. V+ 6 — Positive (highest) power supply V– 2 — Negative (lowest) power supply 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TLV9101 TLV9102 TLV9104 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information for Single Channel 6.5 Thermal Information for Dual Channel 6.6 Thermal Information for Quad Channel 6.7 Electrical Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 EMI Rejection 7.3.2 Phase Reversal Protection 7.3.3 Thermal Protection 7.3.4 Capacitive Load and Stability 7.3.5 Common-Mode Voltage Range 7.3.6 Electrical Overstress 7.3.7 Overload Recovery 7.3.8 Typical Specifications and Distributions 7.3.9 Packages With an Exposed Thermal Pad 7.3.10 Shutdown 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 High Voltage Precision Comparator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curve 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) 11.2 Documentation Support 11.2.1 Related Documentation 11.3 Receiving Notification of Documentation Updates 11.4 Support Resources 11.5 Trademarks 11.6 Electrostatic Discharge Caution 11.7 Glossary 12 Mechanical, Packaging, and Orderable Information