Datasheet MAX4754, MAX4754A, MAX4755, MAX4756, MAX4756A (Maxim) - 10

0.5
Ω
, Quad SPDT Switches in UCSP/QFN Timing Circuits/Timing Diagrams
MAX4754/MAX4754A V+ tr < 5ns MAX4755/MAX4756/ V+ t LOGIC f < 5ns MAX4756A 50% V+ 50% INPUT 0V NO_ COM_ VN_ VOUT OR NC_ R t L OFF CL IN_ VOUT 0.9 x V0UT 0.9 x VOUT LOGIC GND SWITCH 0V INPUT OUTPUT tON CL INCLUDES FIXTURE AND STRAY CAPACITANCE. IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. VOUT = VN_ ( RL ) RL + RON Figure 1. Switching Time V+ MAX4754/MAX4754A V+ MAX4755/MAX4756/ LOGIC 50% V+ INPUT MAX4756A 0V NC_ V V N_ OUT COM_ NO_ RL CL IN_ LOGIC GND INPUT V 0.9 x V OUT OUT tBBM CL INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 2. Break-Before-Make Interval V+ ΔVOUT MAX4754/MAX4754A MAX4755/MAX4756/ V+ VOUT MAX4756A RGEN NC_ COM_ VOUT OR NO_ IN C OFF OFF L V ON GEN GND IN_ ON OFF V OFF IL TO VIH IN Q = (ΔVOUT)(CL)
MAX4754/MAX4754A/MAX4755/MAX4756/MAX4756A
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. Figure 3. Charge Injection
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