Datasheet L6562 (STMicroelectronics) - 8

L6562 Figure 20. Gate-drive clamp vs. T
j
Figure 21. UVLO saturation vs. T
j Vpin7 clamp Vpin7 15 1.1 (V) (V) Vcc = 20 V Vcc = 0 V 1 14 0.9 13 0.8 12 0.7 11 0.6 10 0.5 -50 0 50 100 150 -50 0 50 100 150 Tj (°C) Tj (°C)
4 Application Information 4.1 Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting ripple compo- nents, the current through R1, IR1, equals that through R2, IR2. Considering that the non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV will be 2.5V, then: 2.5 Vo – 2.5 I = ---- = I = ------------- . R2 R2 R1 R1 If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between pins INV and COMP that introduces a long time constant to achieve high PF (this is why ∆Vo can be large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will become: Vo – 2.5 + ∆Vo I' = ----------------------- . R1 R 1 The difference current ∆IR1=I'R1-IR2=I'R1-IR1=∆Vo/R1 will flow through the compensation network and en- ter the error amplifier output (pin COMP). This current is monitored inside the L6562 and if it reaches about 37 µA the output voltage of the multiplier is forced to decrease, thus smoothly reducing the energy deliv- ered to the output. As the current exceeds 40 µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put in an idle state. This condition is main- tained until the current falls below approximately 10 µA, which re-enables the internal starter and allows switching to restart. The output ∆Vo that is able to trigger the Dynamic OVP function is then: ∆ –6 Vo = R 1 ⋅ 40 ⋅ 10 . An important advantage of this technique is that the OV level can be set independently of the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the individual value of R1. Another advantage is the precision: the tolerance of the detection current is 12%, that is 12% tolerance on ∆Vo. Since ∆Vo << Vo, the tolerance on the absolute value will be proportionally reduced. Example: Vo = 400 V, ∆Vo = 40 V. Then: R1=40V/40µA=1MΩ; R2=1MΩ·2.5/(400-2.5)=6.289kΩ. The tol- erance on the OVP level due to the L6562 will be 40·0.12=4.8V, that is 1.2% of the regulated value. 8/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History