Datasheet L6562 (STMicroelectronics)
| Fabricante | STMicroelectronics |
| Descripción | Transition-Mode PFC Controller |
| Páginas / Página | 16 / 1 — L6562. Features. Figure 1. Packages. DIP-8. SO-8. Table 1. Order Codes. … |
| Idioma del documento | Inglés |
L6562. Features. Figure 1. Packages. DIP-8. SO-8. Table 1. Order Codes. Part Number. Package. Description. 1.1 APPLICATIONS
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L6562
TRANSITION-MODE PFC CONTROLLER
1 Features Figure 1. Packages
■ REALISED IN BCD TECHNOLOGY ■ TRANSITION-MODE CONTROL OF PFC PRE- REGULATORS ■ PROPRIETARY MULTIPLIER DESIGN FOR
DIP-8 SO-8
MINIMUM THD OF AC INPUT CURRENT
Table 1. Order Codes
■ VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION
Part Number Package
■ ULTRA-LOW (≤70µA) START-UP CURRENT L6562N DIP-8 ■ LOW (≤4 mA) QUIESCENT CURRENT L6562D SO-8 ■ EXTENDED IC SUPPLY VOLTAGE RANGE L6562DTR Tape & Reel ■ ON-CHIP FILTER ON CURRENT SENSE ■ DISABLE FUNCTION DESKTOP PC, MONITOR) UP TO 300W ■ 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE – HI-END AC-DC ADAPTER/CHARGER – ENTRY LEVEL SERVER & WEB SERVER ■ -600/+800mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN AND VOLTAGE CLAMP
2 Description
■ DIP-8/SO-8 PACKAGES ECOPACK® The L6562 is a current-mode PFC controller oper-
1.1 APPLICATIONS
ating in Transition Mode (TM). Pin-to-pin compati- ■ PFC PRE-REGULATORS FOR: ble with the predecessor L6561, it offers improved performance. – IEC61000-3-2 COMPLIANT SMPS (TV,
Figure 2. Block Diagram
COMP MULT CS 2 3 4 1 INV - MULTIPLIER AND 40K THD OPTIMIZER + 2.5V 5pF VOLTAGE OVERVOLTAGE - + REGULATOR DETECTION VCC 8 VCC INTERNAL SUPPLY 7V R Q 15 V 25 V S R1 7 GD + UVLO DRIVER - R2 Starter VREF2 stop ZERO CURRENT DETECTOR + 2.1 V STARTER - 1.6 V DISABLE 6 5 GND ZCD Rev. 8 November 2005 1/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History
TRANSITION-MODE PFC CONTROLLER
1 Features Figure 1. Packages
■ REALISED IN BCD TECHNOLOGY ■ TRANSITION-MODE CONTROL OF PFC PRE- REGULATORS ■ PROPRIETARY MULTIPLIER DESIGN FOR
DIP-8 SO-8
MINIMUM THD OF AC INPUT CURRENT
Table 1. Order Codes
■ VERY PRECISE ADJUSTABLE OUTPUT OVERVOLTAGE PROTECTION
Part Number Package
■ ULTRA-LOW (≤70µA) START-UP CURRENT L6562N DIP-8 ■ LOW (≤4 mA) QUIESCENT CURRENT L6562D SO-8 ■ EXTENDED IC SUPPLY VOLTAGE RANGE L6562DTR Tape & Reel ■ ON-CHIP FILTER ON CURRENT SENSE ■ DISABLE FUNCTION DESKTOP PC, MONITOR) UP TO 300W ■ 1% (@ Tj = 25 °C) INTERNAL REFERENCE VOLTAGE – HI-END AC-DC ADAPTER/CHARGER – ENTRY LEVEL SERVER & WEB SERVER ■ -600/+800mA TOTEM POLE GATE DRIVER WITH UVLO PULL-DOWN AND VOLTAGE CLAMP
2 Description
■ DIP-8/SO-8 PACKAGES ECOPACK® The L6562 is a current-mode PFC controller oper-
1.1 APPLICATIONS
ating in Transition Mode (TM). Pin-to-pin compati- ■ PFC PRE-REGULATORS FOR: ble with the predecessor L6561, it offers improved performance. – IEC61000-3-2 COMPLIANT SMPS (TV,
Figure 2. Block Diagram
COMP MULT CS 2 3 4 1 INV - MULTIPLIER AND 40K THD OPTIMIZER + 2.5V 5pF VOLTAGE OVERVOLTAGE - + REGULATOR DETECTION VCC 8 VCC INTERNAL SUPPLY 7V R Q 15 V 25 V S R1 7 GD + UVLO DRIVER - R2 Starter VREF2 stop ZERO CURRENT DETECTOR + 2.1 V STARTER - 1.6 V DISABLE 6 5 GND ZCD Rev. 8 November 2005 1/16 Document Outline Figure 1. Packages Table 1. Order Codes 1 Features 1.1 APPLICATIONS 2 Description Figure 2. Block Diagram Table 2. Absolute Maximum Ratings Figure 3. Pin Connection (Top view) Table 3. Thermal Data Table 4. Pin Description Table 5. Electrical Characteristics (Tj = -25 to 125˚C, VCC = 12, CO = 1 nF; unless otherwise specified) 3 Typical Electrical Characteristics Figure 4. Supply current vs. Supply voltage Figure 5. Start-up & UVLO vs. Tj Figure 6. IC consumption vs. Tj Figure 7. Vcc Zener voltage vs. Tj Figure 8. Feedback reference vs. Tj Figure 9. OVP current vs. Tj Figure 10. E/A output clamp levels vs. Tj Figure 11. Delay-to-output vs. Tj Figure 12. Multiplier characteristic Figure 13. Multiplier gain vs. Tj Figure 14. Vcs clamp vs. Tj Figure 15. Start-up timer vs. Tj Figure 16. ZCD clamp levels vs. Tj Figure 17. ZCD source capability vs. Tj Figure 18. Gate-drive output low saturation Figure 19. Gate-drive output high saturation Figure 20. Gate-drive clamp vs. Tj Figure 21. UVLO saturation vs. Tj 4 Application Information 4.1 Overvoltage protection 4.2 THD optimizer circuit Figure 22. THD optimization: standard TM PFC controller (left side) and L6562 (right side) Figure 23. Typical application circuit (250W, Wide-range mains) Figure 24. Demo board (EVAL6562-80W, Wide-range mains): Electrical schematic Figure 25. EVAL6562-80W: PCB and component layout (Top view, real size: 57 x 108 mm) Table 6. EVAL6562N: Evaluation results at full load Table 7. EVAL6562N: Evaluation results at half load Table 8. EVAL6562N: No-load measurements Figure 26. Line filter (not tested for EMI compliance) used for EVAL6562N evaluation 5 Package Information Figure 27. DIP-8 Mechanical Data & Package Dimensions Figure 28. SO-8 Mechanical Data & Package Dimensions 6 Revision History Table 9. Revision History