Datasheet MM74C00, MM74C02, MM74C04 (Fairchild)

MM74C00
October 1987 Revised January 1999
• MM74C02 MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Quad 2-Input NOR Gate • Hex Inverter • MM General Description
All inputs are protected from damage due to static dis- charge by diode clamps to V
7
CC and GND. The MM74C00, MM74C02, and MM74C04 logic gates
4 C04 Quad
employ complementary MOS (CMOS) to achieve wide
Features
power supply operating range, low power consumption, high noise immunity and symmetric controlled rise and fall ■ Wide supply voltage range: 3V to 15V times. With features such as this the 74C logic family is ■ Guaranteed noise margin: 1V close to ideal for use in digital systems. Function and pin ■ High noise immunity: 0.45 V out compatibility with series 74 devices minimizes design CC (typ.) time for those designers already familiar with the standard ■ Low power consumption: 10 nW/package (typ.)
2-I
74 logic family. ■ Low power: TTL compatibility:
nput
Fan out of 2 driving 74L
NAND Gat Ordering Code: Order Number Package Number Package Description
MM74C00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
e
MM74C02N M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
• Quad 2
MM74C04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
-I Connection Diagrams nput Pin Assignments for DIP and SOIC MM74C00 MM74C02 NO R Gate • He x I Top View Top View n ver MM74C04 ter Top View
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