Datasheet AD9731 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | l0-Bit, 170 MSPS, Bipolar D/A Converter |
| Páginas / Página | 12 / 2 — AD9731–SPECIFICATIONS (+VS = +5 V, –VS = –5.2 V, CLOCK = 125 MHz, RSET = … |
| Formato / tamaño de archivo | PDF / 894 Kb |
| Idioma del documento | Inglés |
AD9731–SPECIFICATIONS (+VS = +5 V, –VS = –5.2 V, CLOCK = 125 MHz, RSET = 1.96 k. for 20.4 mA IOUT,
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AD9731–SPECIFICATIONS (+VS = +5 V, –VS = –5.2 V, CLOCK = 125 MHz, RSET = 1.96 k
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for 20.4 mA IOUT, VREF = –1.25 V, unless otherwise noted.) Test Parameter Temp Level Min Typ Max Unit
RESOLUTION 10 Bits MAX CONVERSION RATE –40∞C to +85∞C IV 170 MHz DC ACCURACY Differential Nonlinearity 25∞C I 0.25 1 LSB Full VI 0.35 1.5 LSB Integral Nonlinearity 25∞C I 0.6 1 LSB Full VI 0.7 1.5 LSB INITIAL OFFSET ERROR Zero-Scale Offset Error 25∞C I 35 70 mA Full VI 40 100 mA Full-Scale Gain Error1 25∞C I 2.5 5 % FS Full VI 2.5 5 % FS Offset Drift Coefficient V 0.04 mA/∞C
OBSOLETE
REFERENCE/CONTROL AMP Internal Reference Voltage2 25∞C I –1.35 –1.25 –1.15 V Internal Reference Voltage Drift Full IV 100 mV/∞C Internal Reference Output Current3 Full VI –50 +500 mA Amplifier Input Impedance 25∞C V 50 kW Amplifier Bandwidth 25∞C V 2.5 MHz REFERENCE INPUT4 Reference Input Impedance 25∞C V 4.6 kW Reference Multiplying Bandwidth5 25∞C V 75 MHz OUTPUT PERFORMANCE Output Current4, 6 25∞C V 20 mA Output Compliance 25∞C IV –1.5 +3 V Output Resistance 25∞C V 240 W Output Capacitance 25∞C V 5 pF Voltage Settling Time to 1/2 LSB (tST)7 25∞C V 3.8 ns Propagation Delay (tPD)8 25∞C V 2.9 ns Glitch Impulse9 25∞C V 4.1 pVs Output Slew Rate10 25∞C V 400 V/ms Output Rise Time10 25∞C V 1 ns Output Fall Time10 25∞C V 1 ns DIGITAL INPUTS Input Capacitance Full IV 2 pF Logic “1” Voltage Full VI 2.0 V Logic “0” Voltage Full VI 0.8 V Logic “1” Current 25∞C VI 8 50 mA Logic “0” Current 25∞C VI 30 100 mA Data Setup Time (tS)11 25∞C IV 2 ns Full IV 2.5 ns Data Hold Time (tH)12 25∞C IV 1.0 0.1 ns Full IV 1.0 0.1 ns Clock Pulsewidth Low (pwMIN) 25∞C IV 2 ns Clock Pulsewidth High (pwMAX) 25∞C IV 2 ns SFDR PERFORMANCE (Wideband) 13 AOUT = 0 dBFS 2 MHz fOUT 25∞C V 66 dB 10 MHz fOUT 25∞C V 62 dB 20 MHz fOUT 25∞C V 61 dB 40 MHz fOUT 25∞C V 55 dB 65 MHz fOUT (Clock = 170 MHz) 25∞C V 50 dB 70 MHz fOUT (Clock = 170 MHz) 25∞C V 47 dB –2– REV. B Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION Typical Performance Characteristics THEORY AND APPLICATIONS Digital Inputs/Timing Input Clock and Data Timing Relationship References Analog Output EVALUATION BOARD OUTLINE DIMENSIONS Revision History
⍀
for 20.4 mA IOUT, VREF = –1.25 V, unless otherwise noted.) Test Parameter Temp Level Min Typ Max Unit
RESOLUTION 10 Bits MAX CONVERSION RATE –40∞C to +85∞C IV 170 MHz DC ACCURACY Differential Nonlinearity 25∞C I 0.25 1 LSB Full VI 0.35 1.5 LSB Integral Nonlinearity 25∞C I 0.6 1 LSB Full VI 0.7 1.5 LSB INITIAL OFFSET ERROR Zero-Scale Offset Error 25∞C I 35 70 mA Full VI 40 100 mA Full-Scale Gain Error1 25∞C I 2.5 5 % FS Full VI 2.5 5 % FS Offset Drift Coefficient V 0.04 mA/∞C
OBSOLETE
REFERENCE/CONTROL AMP Internal Reference Voltage2 25∞C I –1.35 –1.25 –1.15 V Internal Reference Voltage Drift Full IV 100 mV/∞C Internal Reference Output Current3 Full VI –50 +500 mA Amplifier Input Impedance 25∞C V 50 kW Amplifier Bandwidth 25∞C V 2.5 MHz REFERENCE INPUT4 Reference Input Impedance 25∞C V 4.6 kW Reference Multiplying Bandwidth5 25∞C V 75 MHz OUTPUT PERFORMANCE Output Current4, 6 25∞C V 20 mA Output Compliance 25∞C IV –1.5 +3 V Output Resistance 25∞C V 240 W Output Capacitance 25∞C V 5 pF Voltage Settling Time to 1/2 LSB (tST)7 25∞C V 3.8 ns Propagation Delay (tPD)8 25∞C V 2.9 ns Glitch Impulse9 25∞C V 4.1 pVs Output Slew Rate10 25∞C V 400 V/ms Output Rise Time10 25∞C V 1 ns Output Fall Time10 25∞C V 1 ns DIGITAL INPUTS Input Capacitance Full IV 2 pF Logic “1” Voltage Full VI 2.0 V Logic “0” Voltage Full VI 0.8 V Logic “1” Current 25∞C VI 8 50 mA Logic “0” Current 25∞C VI 30 100 mA Data Setup Time (tS)11 25∞C IV 2 ns Full IV 2.5 ns Data Hold Time (tH)12 25∞C IV 1.0 0.1 ns Full IV 1.0 0.1 ns Clock Pulsewidth Low (pwMIN) 25∞C IV 2 ns Clock Pulsewidth High (pwMAX) 25∞C IV 2 ns SFDR PERFORMANCE (Wideband) 13 AOUT = 0 dBFS 2 MHz fOUT 25∞C V 66 dB 10 MHz fOUT 25∞C V 62 dB 20 MHz fOUT 25∞C V 61 dB 40 MHz fOUT 25∞C V 55 dB 65 MHz fOUT (Clock = 170 MHz) 25∞C V 50 dB 70 MHz fOUT (Clock = 170 MHz) 25∞C V 47 dB –2– REV. B Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION Typical Performance Characteristics THEORY AND APPLICATIONS Digital Inputs/Timing Input Clock and Data Timing Relationship References Analog Output EVALUATION BOARD OUTLINE DIMENSIONS Revision History