Datasheet MAX6369, MAX6370, MAX6371, MAX6372, MAX6373, MAX6374 (Maxim) - 5

Pin-Selectable Watchdog Timers MAX6369–MAX6374 Pin Description PIN NAME FUNCTION
Watchdog Input. If WDI remains either high or low for the duration of the watchdog timeout period (tWD), WDO 1 WDI triggers a pulse. The internal watchdog timer clears whenever a WDO is asserted or whenever WDI sees a rising or falling edge. 2 GND Ground 3 N.C. Not Connected. Do not make any connection to this pin. 4 SET0 S et Z er o. Log ic i np ut for sel ecti ng star tup d el ay and w atchd og ti meout p er iod s. S ee Tab le 1 for ti ming d etai ls. 5 SET1 S et One. Log ic i np ut for sel ecti ng star tup d el ay and w atchd og ti meout p er iod s. S ee Tab le 1 for ti ming d etai ls. 6 SET2 S et Tw o. Log ic i np ut for sel ecti ng star tup d el ay and w atchd og ti meout p er iod s. S ee Tab le 1 for ti ming d etai ls. Watchdog Output. Pulses low for the watchdog output pulse width, tWDO, when the internal watchdog times 7 WDO out. The MAX6369/MAX6371/MAX6373 have open-drain outputs and require a pull-up resistor. The MAX6370/MAX6372/MAX6374 outputs are push-pull. 8 VCC Supply Voltage (+2.5V to +5.5V)
Table 1. Minimum Timeout Settings LOGIC INPUTS MAX6369/MAX6370 MAX6371/MAX6372 MAX6373/MAX6374 SET2 SET1 SET0 tDELAY, tWD tDELAY = 60s, tWD tDELAY tWD
0 0 0 1ms 1ms 3ms 3ms 0 0 1 10ms 3ms 3s 3s 0 1 0 30ms 10ms 60s 1s 0 1 1 Disabled Disabled Disabled Disabled 1 0 0 100ms 100ms 200µs 30µs 1 0 1 1s 300ms First Edge 1s 1 1 0 10s 3s First Edge 10s 1 1 1 60s 60s 60s 10s
Detailed Description
watchdog timeout period are summarized below (see Table 1 for the timeout characteristics for all devices in The MAX6369–MAX6374 are flexible watchdog circuits the family): for monitoring µP activity. During normal operation, the internal timer is cleared each time the µP toggles the • Watchdog Startup Delay: WDI with a valid logic transition (low to high or high to Provides an initial delay before the watchdog timer is low) within the selected timeout period (tWD). The WDO started. remains high as long as the input is strobed within the Allows time for the µP system to power up and initial- selected timeout period. If the input is not strobed ize before assuming responsibility for normal watch- before the timeout period expires, the watchdog output dog timer updates. is asserted low for the watchdog output pulse width (tWDO). The device type and the state of the three logic Includes several fixed or pin-selectable startup delay control pins (SET0, SET1, and SET2) determine watch- options from 200µs to 60s, and an option to wait for dog timing characteristics. The three basic timing varia- the first watchdog input transition before starting the tions for the watchdog startup delay and the normal watchdog timer.
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