Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 7

eGaN® FET DATASHEET
EPC23102
Output Current Rating
Power stage output current rating is best thought of as a figure To achieve even lower effective thermal resistance, another path is of merit for specified output current level that accounts for the provided from junction to the relatively lower thermal resistance Si maximum amount of power dissipation al owed from the IC. Total substrate of the GaN IC structure to the exposed backside of the entire power dissipation from a power stage IC is tied to the application die at the top of the package to achieve a RθJC_top of 0.4 °C/W. This lower circuit topologies, output current demand, switching frequencies, PCB thermal resistance path facilitates attachment of a topside heatsink construction, operating temperature range, thermal management through thermal interface material (TIM) to the exposed backside of technique and mechanical stress limit of the metal ization imposed the die. Note that the backside of the die is connected to the PGND by electromigration. The rating is related to the respective maximum (=AGND) pins which potential y provides added benefits of using current capability of the two integrated output FETs in the half-bridge electrical y conductive TIM which has >2X higher thermal conductivity power stage but not measured the same way as individual discrete FET. and lower cost than the insulating type. Typical parameters of electrical y For a power stage IC such as EPC23102, total power loss from the IC is conducting vs. insulating TIMs are shown in the table below. the sum of the two output FETs conduction, switching and deadtime losses imposed by the application topologies at operating switching
Typical parameters of electrically conducting vs. insulating TIMs
frequencies as well as power losses from the gate drive and logic circuit.
Type of TIM Thermal Conductivity Relative
The maximum power dissipation is defined by the fol owing formula:
(W/m-K) Cost Electrically Conducting
40 1
Max PDiss = (Max TJ - TA)/ RθJA Electrically Insulating
15 1.3 where Max TJ is specified at 125 °C and the ambient temperature is specified at 25 °C. The big variable in achieving the theoretical Another factor in specifying the output current rating is electromigration maximum power dissipation is R from a metal urgical standpoint. For EPC23102 this limit is a function θJA, the thermal resistance from junction to ambient. The EPC23102 package construction al ows two of the metal ization structure underlying the two output FETs plus paral el path of heat dissipation where the bottom path goes from their connection to the lead-frame and the three exposed power bars. junction to metal ization to lead-frame then the exposed pads at the A maximum of 39 A is al owed due to electromigration limit. bottom of the package. The three power bars (VIN, SW and PGND) are EPC uses a reference evaluation board, EPC90147 as shown in Figure 7, designed to al ow maximum contact area to the underlying PCB pads to configured in a Buck Converter topology with the fol owing test conditions: achieve a RθJB_bottom of 3 °C/W. The total thermal resistance to ambient VIN = 48 V, VOUT = 12 V, PWM frequency = 0.5, 1, and 1.5 MHz, with and in this path of RθJA_bottom needs to add the heat dissipation from the PCB without top side heatsink, airflow = 500 and 1000 LFM, operating at pads through the multi-layer PCB construction then radiating to the ambient temperature starting at 25°C, maximum TC not to exceed 110°C ambient which is highly dependent on the airflow and forced cooling (derated from 125°C to avoid thermal runaway). method. (See Figure 6).
Figure 7: EPC90147 Evaluation Board Figure 6: Parallel Thermal Resistance Paths of EPC23102 IC (see EPC90147 Quick Start Guide f or details) from junction to ambient
TIM: Soft Thermal Pad = Heat path Heatsink r-Global P/N: TB-X 500 µm 200-300 µm compressed thickness RθJC (top) = 0.4 °C/W RθJC (bottom) = 3 °C/W EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 7