Datasheet EFM8SB1 (Silicon Labs) - 5
| Fabricante | Silicon Labs |
| Descripción | EFM8 Sleepy Bee Family |
| Páginas / Página | 71 / 5 — 3. System Overview. 3.1 Introduction. CIP-51 8051 Controller. Port I/O … |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
3. System Overview. 3.1 Introduction. CIP-51 8051 Controller. Port I/O Configuration. Power On. Core. Reset/PMU. Digital Peripherals
Línea de modelo para esta hoja de datos
Versión de texto del documento
EFM8SB1 Data Sheet System Overview
3. System Overview 3.1 Introduction CIP-51 8051 Controller Port I/O Configuration Power On Core Reset/PMU Digital Peripherals Wake 8/4/2 KB ISP Flash UART Program Memory Reset Timers 0, 256 Byte SRAM 1, 2, 3 Port 0
C2CK/RSTb
Debug /
P0.n
Drivers Programming Priority Hardware 256 Byte XRAM PCA/WDT Crossbar Decoder C2D SMBus Port 1
P1.n
Drivers SPI
VDD
SYSCLK VREG CRC Digital Power Crossbar Control Port 2
P2.n
System Clock SFR Driver Configuration Bus Analog Peripherals Precision 24.5 MHz 6-bit Oscillator IREF0 IREF 14-Channel Capacitance
GND
Low Power Internal External To Digital 20 MHz Converter Oscillator VREF VREF VDD VREF XTAL1 External 12-bit Temp Oscillator ADC Sensor AMUX XTAL2 Circuit GND XTAL3 RTC / Low Freq. + XTAL4 Oscillator - Comparator Figure 3.1. Detailed EFM8SB1 Block Diagram
This section describes the EFM8SB1 family at a high level. For more information on each module including register definitions, see the EFM8SB1 Reference Manual.
silabs.com
| Building a more connected world. Rev. 1.4 | 4 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents
3. System Overview 3.1 Introduction CIP-51 8051 Controller Port I/O Configuration Power On Core Reset/PMU Digital Peripherals Wake 8/4/2 KB ISP Flash UART Program Memory Reset Timers 0, 256 Byte SRAM 1, 2, 3 Port 0
C2CK/RSTb
Debug /
P0.n
Drivers Programming Priority Hardware 256 Byte XRAM PCA/WDT Crossbar Decoder C2D SMBus Port 1
P1.n
Drivers SPI
VDD
SYSCLK VREG CRC Digital Power Crossbar Control Port 2
P2.n
System Clock SFR Driver Configuration Bus Analog Peripherals Precision 24.5 MHz 6-bit Oscillator IREF0 IREF 14-Channel Capacitance
GND
Low Power Internal External To Digital 20 MHz Converter Oscillator VREF VREF VDD VREF XTAL1 External 12-bit Temp Oscillator ADC Sensor AMUX XTAL2 Circuit GND XTAL3 RTC / Low Freq. + XTAL4 Oscillator - Comparator Figure 3.1. Detailed EFM8SB1 Block Diagram
This section describes the EFM8SB1 family at a high level. For more information on each module including register definitions, see the EFM8SB1 Reference Manual.
silabs.com
| Building a more connected world. Rev. 1.4 | 4 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents