Datasheet PIC12F629, PIC12F675 (Microchip)
| Fabricante | Microchip |
| Descripción | 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers |
| Páginas / Página | 136 / 1 — PIC12F629/675. Data Sheet |
| Formato / tamaño de archivo | PDF / 1.5 Mb |
| Idioma del documento | Inglés |
PIC12F629/675. Data Sheet
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- PIC12F629-C/P PIC12F629-C/SN PIC12F629-E/MD PIC12F629-E/MF PIC12F629-E/P PIC12F629-E/SN PIC12F629-E/SNVAO PIC12F629-I/MD PIC12F629-I/MF PIC12F629-I/P PIC12F629-I/P PBF PIC12F629-I/SN PIC12F629-I/SN PBF PIC12F629-I/SNG PIC12F629-I/SNVAO PIC12F629T-C/SN PIC12F629T-E/MD PIC12F629T-E/MF PIC12F629T-E/SN PIC12F629T-E/SN226 PIC12F629T-E/SNV08 PIC12F629T-E/SNVAO PIC12F629T-I/MD PIC12F629T-I/MF PIC12F629T-I/SN PIC12F629T-I/SN230 PIC12F629T-I/SNVAO
- PIC12F675-C/P PIC12F675-C/SN PIC12F675-E/MD PIC12F675-E/MF PIC12F675-E/P PIC12F675-E/PG PIC12F675-E/SN PIC12F675-E/SNG PIC12F675-I/MD PIC12F675-I/MF PIC12F675-I/P PIC12F675-I/PG PIC12F675-I/SN PIC12F675-I/SNG PIC12F675-I/SNVAO PIC12F675T-C/SN PIC12F675T-E/MD PIC12F675T-E/MF PIC12F675T-E/SN PIC12F675T-E/SNG PIC12F675T-I/MD PIC12F675T-I/MF PIC12F675T-I/SN PIC12F675T-I/SNG PIC12F675T-I/SNVAO
Versión de texto del documento
PIC12F629/675 Data Sheet
8-Pin, Flash-Based 8-Bit CMOS Microcontrollers 2010 Microchip Technology Inc. DS41190G Document Outline High-Performance RISC CPU: Special Microcontroller Features: Low-Power Features: Peripheral Features: Pin Diagrams Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: PIC12F629/675 Block Diagram TABLE 1-1: PIC12F629/675 Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: Program Memory Map and Stack for the DSTEMP/675 2.2 Data Memory Organization 2.2.1 General Purpose Register File 2.2.2 Special FUNCTION Registers FIGURE 2-2: Data Memory Map of the PIC12F629/675 TABLE 2-1: Special FUNCTION Registers Summary Register 2-1: STATUS: STATUS Register (ADDRESS: 03h or 83h) Register 2-2: OPTION_REG: Option Register (ADDRESS: 81h) Register 2-3: INTCON: Interrupt Control Register (ADDRESS: 0Bh or 8bh) Register 2-4: PIE1: Peripheral Interrupt Enable Register 1 (ADDRESS: 8ch) Register 2-5: PIR1: Peripheral Interrupt Register 1 (ADDRESS: 0ch) Register 2-6: PCON: Power Control Register (ADDRESS: 8Eh) Register 2-7: OSCCAL: Oscillator Calibration Register (ADDRESS: 90h) 2.3 PCL and PCLATH FIGURE 2-3: Loading Of PC In Different Situations 2.3.1 Computed GOTO 2.3.2 Stack 2.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing FIGURE 2-2: Direct/Indirect Addressing PIC12F629/675 3.0 GPIO Port 3.1 GPIO and the TRISIO Registers 3.2 Additional Pin Functions 3.2.1 Weak Pull-up Register 3-1: GPIO: GPIO Register (ADDRESS: 05H) Register 3-2: TRISIO: GPIO Tri-state Register (Address: 85H) Register 3-3: WPU: Weak Pull-up Register (ADDRESS: 95h) 3.2.2 Interrupt-on-change Register 3-4: IOC: Interrupt-on-change GPIO Register (ADDRESS: 96h) 3.3 Pin Descriptions and Diagrams 3.3.1 GP0/AN0/CIN+ 3.3.2 GP1/AN1/CIN-/Vref FIGURE 3-1: Block Diagram of GP0 and GP1 Pins 3.3.3 GP2/AN2/T0CKI/INT/COUT FIGURE 3-2: Block Diagram of GP2 3.3.4 GP3/MCLR/Vpp FIGURE 3-3: Block Diagram of GP3 3.3.5 GP4/AN3/T1G/OSC2/CLKOUT FIGURE 3-4: Block Diagram of GP4 3.3.6 GP5/T1CKI/OSC1/CLKIN FIGURE 3-5: Block Diagram of GP5 TABLE 3-2: Summary of Registers Associated with GPIO 4.0 Timer0 Module 4.1 Timer0 Operation 4.2 Timer0 Interrupt FIGURE 4-1: Block Diagram of thE Timer0/WDT Prescaler 4.3 Using Timer0 with an External Clock Register 4-1: OPTION_REG: Option Register (ADDRESS: 81h) 4.4 Prescaler 4.4.1 Switching Prescaler Assignment TABLE 4-1: Registers Associated with Timer0 5.0 Timer1 Module with Gate Control FIGURE 5-1: TIMER1 BLOCK DIAGRAM 5.1 Timer1 Modes of Operation 5.2 Timer1 Interrupt 5.3 Timer1 Prescaler FIGURE 5-2: TIMER1 INCREMENTING EDGE Register 5-1: T1CON: Timer1 Control Register (ADDRESS: 10h) 5.4 Timer1 Operation in Asynchronous Counter Mode 5.4.1 Reading and Writing Timer1 in Asynchronous Counter Mode 5.5 Timer1 Oscillator 5.6 Timer1 Operation During Sleep TABLE 5-1: Registers Associated with Timer1 as a Timer/Counter 6.0 Comparator Module Register 6-1: CMCON: Comparator Control Register (Address: 19h) 6.1 Comparator Operation TABLE 6-1: Output State vs. Input Conditions FIGURE 6-1: Single Comparator 6.2 Comparator Configuration FIGURE 6-2: Comparator I/O Operating Modes 6.3 Analog Input Connection Considerations FIGURE 6-3: Analog Input Mode 6.4 Comparator Output FIGURE 6-4: Modified Comparator Output Block Diagram 6.5 Comparator Reference 6.5.1 Configuring the Voltage Reference 6.5.2 Voltage Reference Accuracy/Error FIGURE 6-5: Comparator Voltage Reference Block Diagram 6.6 Comparator Response Time 6.7 Operation During Sleep 6.8 Effects of a Reset Register 6-2: VRCON: Voltage Reference Control Register (Address: 99h) 6.9 Comparator Interrupts TABLE 6-2: Registers Associated with Comparator Module 7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) FIGURE 7-1: A/D Block Diagram 7.1 A/D Configuration and Operation 7.1.1 Analog Port Pins 7.1.2 Channel Selection 7.1.3 Voltage Reference 7.1.4 Conversion Clock TABLE 7-1: Tad VS. DEVICE OPERATING FREQUENCIES 7.1.5 Starting a Conversion 7.1.6 Conversion Output FIGURE 7-2: 10-Bit A/D Result Format Register 7-1: ADCON0: A/D Control Register (ADDRESS: 1Fh) Register 7-2: ANSEL: Analog Select Register (ADDRESS: 9Fh) 7.2 A/D Acquisition Requirements FIGURE 7-3: Analog Input Model 7.3 A/D Operation During Sleep 7.4 Effects of Reset TABLE 7-2: Summary of A/D Registers 8.0 Data EEPROM Memory Register 8-1: EEDAT: EEPROM Data Register (ADDRESS: 9ah) Register 8-2: EEADR: EEPROM Address Register (ADDRESS: 9Bh) 8.1 EEADR 8.2 EECON1 and EECON2 Registers Register 8-3: EECON1: EEPROM Control Register (Address: 9Ch) 8.3 Reading the EEPROM Data Memory 8.4 Writing to the EEPROM Data Memory 8.5 Write Verify 8.5.1 Using the Data EEPROM 8.6 Protection Against Spurious Write 8.7 Data EEPROM Operation During Code Protect TABLE 8-1: Registers/Bits Associated with Data EEPROM 9.0 Special Features of the CPU 9.1 Configuration Bits Register 9-1: CONFIG: Configuration Word (ADDRESS: 2007h) 9.2 Oscillator Configurations 9.2.1 Oscillator Types 9.2.2 Crystal Oscillator / Ceramic Resonators FIGURE 9-1: Crystal Operation (or Ceramic Resonator) HS, XT or LP Osc Configuration FIGURE 9-2: External Clock Input Operation (HS, XT, EC, or LP Osc Configuration) TABLE 9-1: Capacitor Selection for Ceramic Resonators TABLE 9-2: Capacitor Selection for Crystal Oscillator 9.2.3 External Clock In 9.2.4 RC Oscillator FIGURE 9-3: RC OSCILLATOR MODE 9.2.5 Internal 4 MHz Oscillator 9.2.6 CLKOUT 9.3 Reset FIGURE 9-4: Simplified Block Diagram of On-chip Reset Circuit 9.3.1 MCLR FIGURE 9-5: Recommended MCLR Circuit 9.3.2 Power-On Reset (POR) 9.3.3 Power-up Timer (PWRT) 9.3.4 Oscillator Start-up Timer (OST) 9.3.5 Brown-Out Detect (BOD) FIGURE 9-6: Brown-out Situations 9.3.6 Time-out Sequence 9.3.7 Power Control (PCON) Status Register TABLE 9-3: Time-out in Various Situations TABLE 9-4: Status/PCON Bits and Their Significance TABLE 9-5: Summary of Registers Associated with Brown-out TABLE 9-6: Initialization Condition for Special Registers TABLE 9-7: Initialization Condition for Registers FIGURE 9-7: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 1 FIGURE 9-8: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 2 FIGURE 9-9: Time-out Sequence on Power-up (MCLR tied to Vdd) 9.4 Interrupts FIGURE 9-10: INTERRUPT LOGIC 9.4.1 GP2/INT Interrupt 9.4.2 TMR0 Interrupt 9.4.3 GPIO Interrupt 9.4.4 Comparator Interrupt 9.4.5 A/D Converter Interrupt FIGURE 9-11: INT Pin Interrupt Timing TABLE 9-8: Summary of interrupt registers 9.5 Context Saving During Interrupts 9.6 Watchdog Timer (WDT) 9.6.1 WDT Period 9.6.2 WDT Programming Considerations FIGURE 9-12: Watchdog Timer Block Diagram TABLE 9-9: Summary of Watchdog Timer Registers 9.7 Power-Down Mode (Sleep) 9.7.1 Wake-up from Sleep FIGURE 9-13: Wake-up from Sleep Through Interrupt 9.8 Code Protection 9.9 ID Locations 9.10 In-Circuit Serial Programming FIGURE 9-14: Typical In-Circuit Serial Programming Connection 9.11 In-Circuit Debugger TABLE 9-10: Debugger Resources 10.0 Instruction Set Summary 10.1 Read-Modify-Write Operations TABLE 10-1: Opcode Field Descriptions FIGURE 10-1: General Format for Instructions TABLE 10-2: PIC12F629/675 Instruction Set 10.2 Instruction Descriptions 11.0 Development Support 11.1 MPLAB Integrated Development Environment Software 11.2 MPLAB C Compilers for Various Device Families 11.3 HI-TECH C for Various Device Families 11.4 MPASM Assembler 11.5 MPLINK Object Linker/ MPLIB Object Librarian 11.6 MPLAB Assembler, Linker and Librarian for Various Device Families 11.7 MPLAB SIM Software Simulator 11.8 MPLAB REAL ICE In-Circuit Emulator System 11.9 MPLAB ICD 3 In-Circuit Debugger System 11.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express 11.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 11.12 MPLAB PM3 Device Programmer 11.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 12.0 Electrical Specifications FIGURE 12-1: PIC12F629/675 With A/D Disabled Voltage-Frequency Graph, -40°C £ ta £ +125°C FIGURE 12-2: PIC12F675 With A/D Enabled Voltage-Frequency Graph, -40°C £ ta £ +125°C FIGURE 12-3: PIC12F675 With A/D Enabled Voltage-Frequency Graph, 0°C £ ta £ +125°C 12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) 12.2 DC Characteristics: PIC12F629/675-I (Industrial) 12.3 DC Characteristics: PIC12F629/675-I (Industrial) 12.4 DC Characteristics: PIC12F629/675-E (Extended) 12.5 DC Characteristics: PIC12F629/675-E (Extended) 12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) 12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.) 12.8 Timing Parameter Symbology FIGURE 12-4: LOAD CONDITIONS 12.9 AC Characteristics: PIC12F629/675 (Industrial, Extended) TABLE 12-1: External Clock Timing Requirements TABLE 12-2: pRECISION INTERNAL OSCILLATOR Parameters TABLE 12-3: CLKOUT and I/O Timing Requirements TABLE 12-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Detect Requirements TABLE 12-5: Timer0 and Timer1 External Clock Requirements TABLE 12-6: Comparator Specifications TABLE 12-7: Comparator Voltage Reference Specifications TABLE 12-8: PIC12F675 A/D Converter Characteristics: TABLE 12-9: PIC12F675 A/D Conversion Requirements TABLE 12-10: PIC12F675 A/D Conversion Requirements (Sleep Mode) 13.0 DC and AC Characteristics Graphs and Tables FIGURE 13-1: Typical Ipd vs. Vdd OVER TEMP (-40°C to +25°C) FIGURE 13-2: Typical Ipd vs. Vdd OVER TEMP (+85°C) FIGURE 13-3: Typical Ipd vs. Vdd OVER TEMP (+125°C) FIGURE 13-4: Maximum Ipd vs. Vdd OVER TEMP (-40°C to +25°C) FIGURE 13-5: Maximum Ipd vs. Vdd OVER TEMP (+85°C) FIGURE 13-6: Maximum Ipd vs. Vdd OVER TEMP (+125°C) FIGURE 13-7: Typical Ipd with BOD Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-8: Typical Ipd with CMP Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-9: Typical Ipd with A/D Enabled vs. Vdd Over Temp (-40°C to +25°C) FIGURE 13-10: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+85°C) FIGURE 13-11: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+125°C) FIGURE 13-12: Typical Ipd with T1 OSC Enabled vs. Vdd Over Temp (-40°C to +125°C), 32 kHz, C1 and C2=50 pF) FIGURE 13-13: Typical Ipd with CVref Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-14: Typical Ipd with WDT Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-15: MAXIMUM and MINIMUM INTOSC FREQ vs. Temperature with 0.1mF and 0.01mF decoupling (Vdd = 3.5V) FIGURE 13-16: MAXIMUM and MINIMUM INTOSC FREQ vs. Vdd with 0.1mF and 0.01mF decoupling (+25°C) FIGURE 13-17: Typical WDT Period vs. Vdd (-40°C to +125°C) 14.0 Packaging Information 14.1 Package Marking Information 14.2 Package Details Appendix A: Data Sheet Revision History Revision A Revision B Revision C Revision D (01/2007) Revision E (03/2007) Revision F (09/2009) Appendix B: Device Differences TABLE B-1: Device Differences Appendix C: Device Migrations Appendix D: Migrating from other PIC® Devices TABLE 1: Feature Comparison The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Product Identification System Worldwide Sales
8-Pin, Flash-Based 8-Bit CMOS Microcontrollers 2010 Microchip Technology Inc. DS41190G Document Outline High-Performance RISC CPU: Special Microcontroller Features: Low-Power Features: Peripheral Features: Pin Diagrams Most Current Data Sheet Errata Customer Notification System 1.0 Device Overview FIGURE 1-1: PIC12F629/675 Block Diagram TABLE 1-1: PIC12F629/675 Pinout Description 2.0 Memory Organization 2.1 Program Memory Organization FIGURE 2-1: Program Memory Map and Stack for the DSTEMP/675 2.2 Data Memory Organization 2.2.1 General Purpose Register File 2.2.2 Special FUNCTION Registers FIGURE 2-2: Data Memory Map of the PIC12F629/675 TABLE 2-1: Special FUNCTION Registers Summary Register 2-1: STATUS: STATUS Register (ADDRESS: 03h or 83h) Register 2-2: OPTION_REG: Option Register (ADDRESS: 81h) Register 2-3: INTCON: Interrupt Control Register (ADDRESS: 0Bh or 8bh) Register 2-4: PIE1: Peripheral Interrupt Enable Register 1 (ADDRESS: 8ch) Register 2-5: PIR1: Peripheral Interrupt Register 1 (ADDRESS: 0ch) Register 2-6: PCON: Power Control Register (ADDRESS: 8Eh) Register 2-7: OSCCAL: Oscillator Calibration Register (ADDRESS: 90h) 2.3 PCL and PCLATH FIGURE 2-3: Loading Of PC In Different Situations 2.3.1 Computed GOTO 2.3.2 Stack 2.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-1: Indirect Addressing FIGURE 2-2: Direct/Indirect Addressing PIC12F629/675 3.0 GPIO Port 3.1 GPIO and the TRISIO Registers 3.2 Additional Pin Functions 3.2.1 Weak Pull-up Register 3-1: GPIO: GPIO Register (ADDRESS: 05H) Register 3-2: TRISIO: GPIO Tri-state Register (Address: 85H) Register 3-3: WPU: Weak Pull-up Register (ADDRESS: 95h) 3.2.2 Interrupt-on-change Register 3-4: IOC: Interrupt-on-change GPIO Register (ADDRESS: 96h) 3.3 Pin Descriptions and Diagrams 3.3.1 GP0/AN0/CIN+ 3.3.2 GP1/AN1/CIN-/Vref FIGURE 3-1: Block Diagram of GP0 and GP1 Pins 3.3.3 GP2/AN2/T0CKI/INT/COUT FIGURE 3-2: Block Diagram of GP2 3.3.4 GP3/MCLR/Vpp FIGURE 3-3: Block Diagram of GP3 3.3.5 GP4/AN3/T1G/OSC2/CLKOUT FIGURE 3-4: Block Diagram of GP4 3.3.6 GP5/T1CKI/OSC1/CLKIN FIGURE 3-5: Block Diagram of GP5 TABLE 3-2: Summary of Registers Associated with GPIO 4.0 Timer0 Module 4.1 Timer0 Operation 4.2 Timer0 Interrupt FIGURE 4-1: Block Diagram of thE Timer0/WDT Prescaler 4.3 Using Timer0 with an External Clock Register 4-1: OPTION_REG: Option Register (ADDRESS: 81h) 4.4 Prescaler 4.4.1 Switching Prescaler Assignment TABLE 4-1: Registers Associated with Timer0 5.0 Timer1 Module with Gate Control FIGURE 5-1: TIMER1 BLOCK DIAGRAM 5.1 Timer1 Modes of Operation 5.2 Timer1 Interrupt 5.3 Timer1 Prescaler FIGURE 5-2: TIMER1 INCREMENTING EDGE Register 5-1: T1CON: Timer1 Control Register (ADDRESS: 10h) 5.4 Timer1 Operation in Asynchronous Counter Mode 5.4.1 Reading and Writing Timer1 in Asynchronous Counter Mode 5.5 Timer1 Oscillator 5.6 Timer1 Operation During Sleep TABLE 5-1: Registers Associated with Timer1 as a Timer/Counter 6.0 Comparator Module Register 6-1: CMCON: Comparator Control Register (Address: 19h) 6.1 Comparator Operation TABLE 6-1: Output State vs. Input Conditions FIGURE 6-1: Single Comparator 6.2 Comparator Configuration FIGURE 6-2: Comparator I/O Operating Modes 6.3 Analog Input Connection Considerations FIGURE 6-3: Analog Input Mode 6.4 Comparator Output FIGURE 6-4: Modified Comparator Output Block Diagram 6.5 Comparator Reference 6.5.1 Configuring the Voltage Reference 6.5.2 Voltage Reference Accuracy/Error FIGURE 6-5: Comparator Voltage Reference Block Diagram 6.6 Comparator Response Time 6.7 Operation During Sleep 6.8 Effects of a Reset Register 6-2: VRCON: Voltage Reference Control Register (Address: 99h) 6.9 Comparator Interrupts TABLE 6-2: Registers Associated with Comparator Module 7.0 Analog-to-Digital Converter (A/D) Module (PIC12F675 only) FIGURE 7-1: A/D Block Diagram 7.1 A/D Configuration and Operation 7.1.1 Analog Port Pins 7.1.2 Channel Selection 7.1.3 Voltage Reference 7.1.4 Conversion Clock TABLE 7-1: Tad VS. DEVICE OPERATING FREQUENCIES 7.1.5 Starting a Conversion 7.1.6 Conversion Output FIGURE 7-2: 10-Bit A/D Result Format Register 7-1: ADCON0: A/D Control Register (ADDRESS: 1Fh) Register 7-2: ANSEL: Analog Select Register (ADDRESS: 9Fh) 7.2 A/D Acquisition Requirements FIGURE 7-3: Analog Input Model 7.3 A/D Operation During Sleep 7.4 Effects of Reset TABLE 7-2: Summary of A/D Registers 8.0 Data EEPROM Memory Register 8-1: EEDAT: EEPROM Data Register (ADDRESS: 9ah) Register 8-2: EEADR: EEPROM Address Register (ADDRESS: 9Bh) 8.1 EEADR 8.2 EECON1 and EECON2 Registers Register 8-3: EECON1: EEPROM Control Register (Address: 9Ch) 8.3 Reading the EEPROM Data Memory 8.4 Writing to the EEPROM Data Memory 8.5 Write Verify 8.5.1 Using the Data EEPROM 8.6 Protection Against Spurious Write 8.7 Data EEPROM Operation During Code Protect TABLE 8-1: Registers/Bits Associated with Data EEPROM 9.0 Special Features of the CPU 9.1 Configuration Bits Register 9-1: CONFIG: Configuration Word (ADDRESS: 2007h) 9.2 Oscillator Configurations 9.2.1 Oscillator Types 9.2.2 Crystal Oscillator / Ceramic Resonators FIGURE 9-1: Crystal Operation (or Ceramic Resonator) HS, XT or LP Osc Configuration FIGURE 9-2: External Clock Input Operation (HS, XT, EC, or LP Osc Configuration) TABLE 9-1: Capacitor Selection for Ceramic Resonators TABLE 9-2: Capacitor Selection for Crystal Oscillator 9.2.3 External Clock In 9.2.4 RC Oscillator FIGURE 9-3: RC OSCILLATOR MODE 9.2.5 Internal 4 MHz Oscillator 9.2.6 CLKOUT 9.3 Reset FIGURE 9-4: Simplified Block Diagram of On-chip Reset Circuit 9.3.1 MCLR FIGURE 9-5: Recommended MCLR Circuit 9.3.2 Power-On Reset (POR) 9.3.3 Power-up Timer (PWRT) 9.3.4 Oscillator Start-up Timer (OST) 9.3.5 Brown-Out Detect (BOD) FIGURE 9-6: Brown-out Situations 9.3.6 Time-out Sequence 9.3.7 Power Control (PCON) Status Register TABLE 9-3: Time-out in Various Situations TABLE 9-4: Status/PCON Bits and Their Significance TABLE 9-5: Summary of Registers Associated with Brown-out TABLE 9-6: Initialization Condition for Special Registers TABLE 9-7: Initialization Condition for Registers FIGURE 9-7: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 1 FIGURE 9-8: Time-out Sequence on Power-up (MCLR not tied to Vdd): Case 2 FIGURE 9-9: Time-out Sequence on Power-up (MCLR tied to Vdd) 9.4 Interrupts FIGURE 9-10: INTERRUPT LOGIC 9.4.1 GP2/INT Interrupt 9.4.2 TMR0 Interrupt 9.4.3 GPIO Interrupt 9.4.4 Comparator Interrupt 9.4.5 A/D Converter Interrupt FIGURE 9-11: INT Pin Interrupt Timing TABLE 9-8: Summary of interrupt registers 9.5 Context Saving During Interrupts 9.6 Watchdog Timer (WDT) 9.6.1 WDT Period 9.6.2 WDT Programming Considerations FIGURE 9-12: Watchdog Timer Block Diagram TABLE 9-9: Summary of Watchdog Timer Registers 9.7 Power-Down Mode (Sleep) 9.7.1 Wake-up from Sleep FIGURE 9-13: Wake-up from Sleep Through Interrupt 9.8 Code Protection 9.9 ID Locations 9.10 In-Circuit Serial Programming FIGURE 9-14: Typical In-Circuit Serial Programming Connection 9.11 In-Circuit Debugger TABLE 9-10: Debugger Resources 10.0 Instruction Set Summary 10.1 Read-Modify-Write Operations TABLE 10-1: Opcode Field Descriptions FIGURE 10-1: General Format for Instructions TABLE 10-2: PIC12F629/675 Instruction Set 10.2 Instruction Descriptions 11.0 Development Support 11.1 MPLAB Integrated Development Environment Software 11.2 MPLAB C Compilers for Various Device Families 11.3 HI-TECH C for Various Device Families 11.4 MPASM Assembler 11.5 MPLINK Object Linker/ MPLIB Object Librarian 11.6 MPLAB Assembler, Linker and Librarian for Various Device Families 11.7 MPLAB SIM Software Simulator 11.8 MPLAB REAL ICE In-Circuit Emulator System 11.9 MPLAB ICD 3 In-Circuit Debugger System 11.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express 11.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 11.12 MPLAB PM3 Device Programmer 11.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 12.0 Electrical Specifications FIGURE 12-1: PIC12F629/675 With A/D Disabled Voltage-Frequency Graph, -40°C £ ta £ +125°C FIGURE 12-2: PIC12F675 With A/D Enabled Voltage-Frequency Graph, -40°C £ ta £ +125°C FIGURE 12-3: PIC12F675 With A/D Enabled Voltage-Frequency Graph, 0°C £ ta £ +125°C 12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) 12.2 DC Characteristics: PIC12F629/675-I (Industrial) 12.3 DC Characteristics: PIC12F629/675-I (Industrial) 12.4 DC Characteristics: PIC12F629/675-E (Extended) 12.5 DC Characteristics: PIC12F629/675-E (Extended) 12.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) 12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Cont.) 12.8 Timing Parameter Symbology FIGURE 12-4: LOAD CONDITIONS 12.9 AC Characteristics: PIC12F629/675 (Industrial, Extended) TABLE 12-1: External Clock Timing Requirements TABLE 12-2: pRECISION INTERNAL OSCILLATOR Parameters TABLE 12-3: CLKOUT and I/O Timing Requirements TABLE 12-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer, and Brown-out Detect Requirements TABLE 12-5: Timer0 and Timer1 External Clock Requirements TABLE 12-6: Comparator Specifications TABLE 12-7: Comparator Voltage Reference Specifications TABLE 12-8: PIC12F675 A/D Converter Characteristics: TABLE 12-9: PIC12F675 A/D Conversion Requirements TABLE 12-10: PIC12F675 A/D Conversion Requirements (Sleep Mode) 13.0 DC and AC Characteristics Graphs and Tables FIGURE 13-1: Typical Ipd vs. Vdd OVER TEMP (-40°C to +25°C) FIGURE 13-2: Typical Ipd vs. Vdd OVER TEMP (+85°C) FIGURE 13-3: Typical Ipd vs. Vdd OVER TEMP (+125°C) FIGURE 13-4: Maximum Ipd vs. Vdd OVER TEMP (-40°C to +25°C) FIGURE 13-5: Maximum Ipd vs. Vdd OVER TEMP (+85°C) FIGURE 13-6: Maximum Ipd vs. Vdd OVER TEMP (+125°C) FIGURE 13-7: Typical Ipd with BOD Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-8: Typical Ipd with CMP Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-9: Typical Ipd with A/D Enabled vs. Vdd Over Temp (-40°C to +25°C) FIGURE 13-10: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+85°C) FIGURE 13-11: Typical Ipd with A/D Enabled vs. Vdd Over Temp (+125°C) FIGURE 13-12: Typical Ipd with T1 OSC Enabled vs. Vdd Over Temp (-40°C to +125°C), 32 kHz, C1 and C2=50 pF) FIGURE 13-13: Typical Ipd with CVref Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-14: Typical Ipd with WDT Enabled vs. Vdd Over Temp (-40°C to +125°C) FIGURE 13-15: MAXIMUM and MINIMUM INTOSC FREQ vs. Temperature with 0.1mF and 0.01mF decoupling (Vdd = 3.5V) FIGURE 13-16: MAXIMUM and MINIMUM INTOSC FREQ vs. Vdd with 0.1mF and 0.01mF decoupling (+25°C) FIGURE 13-17: Typical WDT Period vs. Vdd (-40°C to +125°C) 14.0 Packaging Information 14.1 Package Marking Information 14.2 Package Details Appendix A: Data Sheet Revision History Revision A Revision B Revision C Revision D (01/2007) Revision E (03/2007) Revision F (09/2009) Appendix B: Device Differences TABLE B-1: Device Differences Appendix C: Device Migrations Appendix D: Migrating from other PIC® Devices TABLE 1: Feature Comparison The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Product Identification System Worldwide Sales