Datasheet DS2423 (Maxim) - 8

DS2423
Read Memory [F0H]
The read memory command may be used to read the entire memory. After issuing the command, the master must provide the 2-byte target address. After the two bytes, the master reads data beginning from the target address and may continue until the end of memory, at which point logic 1s will be read. It is important to realize that the target address registers will contain the address provided. The ending offset/data status byte is unaffected. The hardware of the DS2423 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Application Note 114 for the recommended file structure.)
Read Memory + Counter [A5H]
The Read Memory + Counter command is used to read memory data together with the write cycle counter or externally triggered counter associated with the addressed page of data memory. The additional information is transmitted by the DS2423 as the end of a memory page is encountered. Following the current value of the counter the DS2423 transmits 32 0-bits and a 16-bit CRC generated by the DS2423. After having sent the command code of the Read Memory + Counter command, the bus master sends a two-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data field. With the subsequent read data time slots the master receives data from the DS2423 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send 80 additional read data time slots and receive the contents of the 32-bit counter associated with the addressed page, 32 0-bits and a 16-bit CRC. With subsequent read data time slots the master will receive data starting at the beginning of the next page followed by the contents of the counter associated with the page, 0-bits and CRC for that page. This sequence will continue until the final page and its accompanying data is read by the bus master. When applying the Read Memory + Counter command to a page that does not have a counter associated, the master will read FFFFFFFFH instead of a valid count. With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes, the contents of the data memory, the counter and the 0-bits. Subsequent passes through the Read Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the contents of the data memory page, its associated counter and 0-bits. After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2423 until a Reset Pulse is issued. The Read Memory + Counter command sequence can be ended at any point by issuing a Reset Pulse.
Not Recommended for New Design
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