Datasheet ADG714, ADG715 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | CMOS, Low Voltage Serially Controlled, Octal SPST Switches |
| Páginas / Página | 21 / 8 — ADG714/. ADG715. Data Sheet. Parameter. Limit at TMIN, TMAX. Unit. … |
| Revisión | E |
| Formato / tamaño de archivo | PDF / 368 Kb |
| Idioma del documento | Inglés |
ADG714/. ADG715. Data Sheet. Parameter. Limit at TMIN, TMAX. Unit. Conditions/Comments. Timing Diagrams. t10. SCLK. t11. SYNC. DIN. DB7. DB0. DOUT
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ADG714/ ADG715 Data Sheet Parameter Limit at TMIN, TMAX Unit Conditions/Comments
Cb 400 pF max Capacitive load for each bus line t 3 SP 50 ns max Pulse width of spike suppressed 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 2 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 × VDD and 0.7 × VDD. 3 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Timing Diagrams t1 t10 SCLK t8 t t 3 2 t11 t t 4 7 SYNC t6 t5 DIN DB7 DB0 t9 DOUT DB7* DB6* DB2* DB1* DB0*
003
*DATA FROM PREVIOUS WRITE CYCLE
00043- Figure 3. 3-Wire Serial Interface Timing Diagram
SDA t t 9 3 t t 11 4 t10 SCL t2 t4 t t t t t 6 5 7 1 8 START REPEATED STOP
004
CONDITION START CONDITION CONDITION
00043- Figure 4. 2-Wire Serial Interface Timing Diagram Rev. E | Page 8 of 21 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications 5 V Single Supply 3 V Single Supply ±2.5 V Dual Supply Timing Characteristics ADG714 ADG715 Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Power-On Reset Serial Interface 3-Wire Serial Interface 2-Wire Serial Interface Input Shift Register Write Operation Read Operation Applications Information Multiple Devices on One Bus Daisy-Chaining Multiple ADG714 Devices Power Supply Sequencing Decoding Multiple ADG714 Devices Using the ADG739 Outline Dimensions Ordering Guide
Cb 400 pF max Capacitive load for each bus line t 3 SP 50 ns max Pulse width of spike suppressed 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. 2 Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 × VDD and 0.7 × VDD. 3 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Timing Diagrams t1 t10 SCLK t8 t t 3 2 t11 t t 4 7 SYNC t6 t5 DIN DB7 DB0 t9 DOUT DB7* DB6* DB2* DB1* DB0*
003
*DATA FROM PREVIOUS WRITE CYCLE
00043- Figure 3. 3-Wire Serial Interface Timing Diagram
SDA t t 9 3 t t 11 4 t10 SCL t2 t4 t t t t t 6 5 7 1 8 START REPEATED STOP
004
CONDITION START CONDITION CONDITION
00043- Figure 4. 2-Wire Serial Interface Timing Diagram Rev. E | Page 8 of 21 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications 5 V Single Supply 3 V Single Supply ±2.5 V Dual Supply Timing Characteristics ADG714 ADG715 Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Power-On Reset Serial Interface 3-Wire Serial Interface 2-Wire Serial Interface Input Shift Register Write Operation Read Operation Applications Information Multiple Devices on One Bus Daisy-Chaining Multiple ADG714 Devices Power Supply Sequencing Decoding Multiple ADG714 Devices Using the ADG739 Outline Dimensions Ordering Guide