link to page 8 link to page 8 ADG1438/ADG1439Data SheetABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum Table 8. Ratings may cause permanent damage to the product. This is a ParameterRating stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational VDD to VSS 35 V section of this specification is not implied. Operation beyond VDD to GND −0.3 V to +25 V the maximum operating conditions for extended periods may VSS to GND +0.3 V to −25 V affect product reliability. VL to GND −0.3 V to +7 V Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or Only one absolute maximum rating can be applied at any one time. 30 mA, whichever occurs first Digital Inputs1 GND − 0.3 V to V THERMAL RESISTANCE L + 0.3 V or 30 mA, whichever occurs first Table 9. Thermal Resistance Continuous Current, Sx or Table 5 and Table 6 specifica- Dx Pins tions + 15% Package TypeθJAθJCUnit Peak Current, Sx or Dx Pins 20 Lead TSSOP (4-Layer Board) 112.6 50 °C/W (Pulsed at 1 ms, 10% Duty 20-Lead LFCSP (4-Layer Board and 30.4 N/A1 °C/W Cycle Max) Exposed Paddle Soldered to VSS) TSSOP 300 mA 1 N/A means not applicable. LFCSP 400 mA Operating Temperature Range ESD CAUTION Industrial (B Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C Reflow Soldering Peak 260(+0/−5)°C Temperature (Pb-Free) Time at Peak Temperature 10 sec to 40 sec 1 Overvoltages at the analog and digital inputs are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B | Page 10 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY ±5 V DUAL SUPPLY CONTINUOUS CURRENT PER CHANNEL TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION SERIAL INTERFACE INPUT SHIFT REGISTER POWER-ON RESET DAISY-CHAINING OUTLINE DIMENSIONS ORDERING GUIDE