Datasheet ADGS1212 (Analog Devices) - 10

ADGS1212 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS K C DI CL DO C NI S S CS S NI 24 23 22 21 20 19 NIC 1 18 NIC GND 2 17 RESET/VL D1 3 ADGS1212 16 NIC S1 4 TOP VIEW 15 D2 (Not to Scale) VSS 5 14 S2 GND 6 13 VDD 7 8 9 10 11 12 S4 D4 C C NI NI D3 S3 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS.
005
2. NIC = NOT INTERNALLY CONNECTED.
15936- Figure 5. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1, 9, 10, 16, NIC Not Internally Connected. 18, 19, 24 2, 6 GND Ground (0 V) Reference. 3 D1 Drain Terminal 1. This pin can be an input or output. 4 S1 Source Terminal 1. This pin can be an input or output. 5 VSS Most Negative Power Supply Potential. In single-supply applications, tie VSS to GND. 7 S4 Source Terminal 4. This pin can be an input or output. 8 D4 Drain Terminal 4. This pin can be an input or output. 11 D3 Drain Terminal 3. This pin can be an input or output. 12 S3 Source Terminal 3. This pin can be an input or output. 13 VDD Most Positive Power Supply Potential. 14 S2 Source Terminal 2. This pin can be an input or output. 15 D2 Drain Terminal 2. This pin can be an input or output. 17 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers are set to their default values. 20 SDO Serial Data Output. This pin can be used for daisy chaining a number of devices together or for reading back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK. Pull this open-drain output to VL with an external resistor. 21 CS Active Low Control Input. CS is the frame synchronization signal for the input data. 22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz. 23 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input. EPAD Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS. Rev. 0 | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Four Channels On One Channel On TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE