Datasheet ADGS1212 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | SPI Interface, Quad SPST Switch, Low QINJ, Low CON, ±15 V/+12 V, Mux Configurable |
| Páginas / Página | 24 / 7 — Data Sheet. ADGS1212. TIMING CHARACTERISTICS. Table 5. Parameter. Limit. … |
| Formato / tamaño de archivo | PDF / 655 Kb |
| Idioma del documento | Inglés |
Data Sheet. ADGS1212. TIMING CHARACTERISTICS. Table 5. Parameter. Limit. Unit. Test Conditions/Comments. Timing Diagrams. SCLK. SDI. R/W. SDO
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Data Sheet ADGS1212 TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization but not production tested.
Table 5. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS t1 20 ns min SCLK period t2 8 ns min SCLK high pulse width t3 8 ns min SCLK low pulse width t4 10 ns min CS falling edge to SCLK active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK becomes stable t13 8 ns min CS rising edge to SCLK becomes stable 1 Measured with the 1 kΩ pull-up resistor to VL and a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams t1 SCLK t2 t t t 4 3 7 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
02 0 6-
t8
593 1 Figure 2. Address Mode Timing Diagram Rev. 0 | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Four Channels On One Channel On TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization but not production tested.
Table 5. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS t1 20 ns min SCLK period t2 8 ns min SCLK high pulse width t3 8 ns min SCLK low pulse width t4 10 ns min CS falling edge to SCLK active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK becomes stable t13 8 ns min CS rising edge to SCLK becomes stable 1 Measured with the 1 kΩ pull-up resistor to VL and a 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams t1 SCLK t2 t t t 4 3 7 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
02 0 6-
t8
593 1 Figure 2. Address Mode Timing Diagram Rev. 0 | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Four Channels On One Channel On TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE