Datasheet ADGS1208, ADGS1209 (Analog Devices) - 10

ADGS1208/ ADGS1209 Data Sheet t1 SCLK t t2 3 t4 t7 CS t t 6 5 SDI D7 D6 D0 D7 D6 D1 D0 INPUT BYTE FOR DEVICE N INPUT BYTE FOR DEVICE N + 1 t t10 9 SDO 0 0 0 D7 D6 D1 D0
103
ZERO BYTE INPUT BYTE FOR DEVICE N t8
16724- Figure 4. Daisy Chain Timing Diagram
t11 CS SCLK OR CNV
004
t t 13 12
16724- Figure 5. SCLK or CNV and CS Timing Diagram
t4 CS t t 2 3 t7 CNV t t 1 9 t10 RESYNC SDO MUX
006
S1 S2 S(LAST) CHANNEL
16724- Figure 6. Round Robin Timing Diagram Rev. 0 | Page 10 of 33 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Round Robin Mode General-Purpose Outputs Applications Information Digital Input Buffers Settling Time Power Supply Rails Power Supply Recommendations Register Summaries Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Round Robin Enable Register Round Robin Channel Configuration Register CNV Edge Select Register Software Reset Register Outline Dimensions Ordering Guide