Datasheet STM32L412xx (STMicroelectronics)

STM32L412xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS, up to 128KB Flash, 40KB SRAM, analog, ext. SMPS
Datasheet
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production data Features
• Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply LQFP32 (7x7 mm) UFBGA64 (5x5 mm) UFQFPN32 (5x5 mm) WLCSP36 (2.6x3.1 mm) – -40 °C to 85/125 °C temperature range LQFP48 (7x7 mm) UFQFPN48 (7x7 mm) LQFP64 (10x10 mm) – 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers – PLL for system clock – 16 nA Shutdown mode (4 wakeup pins) • Up to 52 fast I/Os, most 5 V-tolerant – 32 nA Standby mode (4 wakeup pins) • RTC with HW calendar, alarms and calibration – 245 nA Standby mode with RTC • Up to 12 capacitive sensing channels: support – 0.7 µA Stop 2 mode, 0.95 µA with RTC touchkey, linear and rotary touch sensors – 79 µA/MHz run mode (LDO Mode) • 10x timers: 1x 16-bit advanced motor-control, – 28 μA/MHz run mode (@3.3 V SMPS 1x 32-bit and 2x 16-bit general purpose, 1x 16- Mode) bit basic, 2x low-power 16-bit timers (available – Batch acquisition mode (BAM) in Stop mode), 2x watchdogs, SysTick timer – 4 µs wakeup from Stop mode • Memories – Brown out reset (BOR) – 128 KB single bank Flash, proprietary code – Interconnect matrix readout protection • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, – 40 KB of SRAM including 8 KB with Adaptive real-time accelerator (ART hardware parity check Accelerator™) allowing 0-wait-state execution – Quad SPI memory interface with XIP from Flash memory, frequency up to 80 MHz, capability MPU, 100DMIPS and DSP instructions • Rich analog peripherals (independent supply) • Performance benchmark – 2x 12-bit ADC 5 Msps, up to 16-bit with – 1.25 DMIPS/MHz (Drystone 2.1) hardware oversampling, 200 µA/Msps – 273.55 CoreMark® (3.42 CoreMark/MHz @ – 2x operational amplifiers with built-in PGA 80 MHz) – 1x ultra-low-power comparator • Energy benchmark – Accurate 2.5 V or 2.048 V reference – 442 ULPMark-CP® voltage buffered output – 165 ULPMark-PP® • 12x communication interfaces • Clock Sources – USB 2.0 full-speed crystal less solution – 4 to 48 MHz crystal oscillator with LPM and BCD – 32 kHz crystal oscillator for RTC (LSE) – 3 x I2C FM+( 1 Mbit/s), SMBus/PMBus – Internal 16 MHz factory-trimmed RC (±1%) – 3x USARTs (ISO 7816, LIN, IrDA, modem) – Internal low-power 32 kHz RC (±5%) – 1x LPUART (Stop 2 wake-up) – Internal multispeed 100 kHz to 48 MHz – 2x SPIs (and 1x Quad SPI) oscillator, auto-trimmed by LSE (better than – IRTIM (Infrared interface) ±0.25 % accuracy) • 14-channel DMA controller – Internal 48 MHz with clock recovery • True random number generator November 2020 DS12469 Rev 8 1/192 This is information on a product in full production. www.st.com Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. STM32L412xx family device features and peripheral counts Figure 1. STM32L412xx block diagram 3 Functional overview 3.1 Arm® Cortex®-M4 core with FPU 3.2 Adaptive real-time memory accelerator (ART Accelerator™) 3.3 Memory protection unit 3.4 Embedded Flash memory Table 3. Access status versus readout protection level and execution modes 3.5 Embedded SRAM 3.6 Firewall 3.7 Boot modes 3.8 Cyclic redundancy check calculation unit (CRC) 3.9 Power supply management 3.9.1 Power supply schemes Figure 2. Power supply overview Figure 3. Power-up/down sequence 3.9.2 Power supply supervisor 3.9.3 Voltage regulator 3.9.4 Low-power modes Table 4. STM32L412xx modes overview Table 5. Functionalities depending on the working mode 3.9.5 Reset mode 3.9.6 VBAT operation 3.10 Interconnect matrix Table 6. STM32L412xx peripherals interconnect matrix 3.11 Clocks and startup Figure 4. Clock tree 3.12 General-purpose inputs/outputs (GPIOs) 3.13 Direct memory access controller (DMA) Table 7. DMA implementation 3.14 Interrupts and events 3.14.1 Nested vectored interrupt controller (NVIC) 3.14.2 Extended interrupt/event controller (EXTI) 3.15 Analog to digital converter (ADC) 3.15.1 Temperature sensor Table 8. Temperature sensor calibration values 3.15.2 Internal voltage reference (VREFINT) Table 9. Internal voltage reference calibration values 3.15.3 VBAT battery voltage monitoring 3.16 Comparators (COMP) 3.17 Operational amplifier (OPAMP) 3.18 Touch sensing controller (TSC) 3.19 Random number generator (RNG) 3.20 Timers and watchdogs Table 10. Timer feature comparison 3.20.1 Advanced-control timer (TIM1) 3.20.2 General-purpose timers (TIM2, TIM15, TIM16) 3.20.3 Basic timer (TIM6) 3.20.4 Low-power timer (LPTIM1 and LPTIM2) 3.20.5 Infrared interface (IRTIM) 3.20.6 Independent watchdog (IWDG) 3.20.7 System window watchdog (WWDG) 3.20.8 SysTick timer 3.21 Real-time clock (RTC) and backup registers 3.22 Inter-integrated circuit interface (I2C) Table 11. I2C implementation 3.23 Universal synchronous/asynchronous receiver transmitter (USART) Table 12. STM32L412xx USART/UART/LPUART features 3.24 Low-power universal asynchronous receiver transmitter (LPUART) 3.25 Serial peripheral interface (SPI) 3.26 Universal serial bus (USB) 3.27 Clock recovery system (CRS) 3.28 Quad SPI memory interface (QUADSPI) 3.29 Development support 3.29.1 Serial wire JTAG debug port (SWJ-DP) 3.29.2 Embedded Trace Macrocell™ 4 Pinouts and pin description Figure 5. STM32L412Rx LQFP64 pinout(1) Figure 6. STM32L412Rx, external SMPS, LQFP64 pinout(1) Figure 7. STM32L412Rx UFBGA64 ballout(1) Figure 8. STM32L412Rx UFBGA64, external SMPS, ballout(1) Figure 9. STM32L412Cx LQFP48 pinout(1) Figure 10. STM32L412Cx UFQFPN48 pinout(1) Figure 11. STM32L412Tx WLCSP36 ballout(1) Figure 12. STM32L412Tx, external SMPS, WLCSP36 ballout(1) Figure 13. STM32L412Kx LQFP32 pinout(1) Figure 14. STM32L412Kx UFQFPN32 pinout(1) Table 13. Legend/abbreviations used in the pinout table Table 14. STM32L412xx pin definitions Table 15. Alternate function AF0 to AF7 Table 16. Alternate function AF8 to AF15 5 Memory mapping Figure 15. STM32L412xx memory map Table 17. STM32L412xx memory map and peripheral register boundary addresses 6 Electrical characteristics 6.1 Parameter conditions 6.1.1 Minimum and maximum values 6.1.2 Typical values 6.1.3 Typical curves 6.1.4 Loading capacitor 6.1.5 Pin input voltage Figure 16. Pin loading conditions Figure 17. Pin input voltage 6.1.6 Power supply scheme Figure 18. Power supply scheme 6.1.7 Current consumption measurement Figure 19. Current consumption measurement scheme with and without external SMPS power supply 6.2 Absolute maximum ratings Table 18. Voltage characteristics Table 19. Current characteristics Table 20. Thermal characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 21. General operating conditions 6.3.2 Operating conditions at power-up / power-down Table 22. Operating conditions at power-up / power-down 6.3.3 Embedded reset and power control block characteristics Table 23. Embedded reset and power control block characteristics 6.3.4 Embedded voltage reference Table 24. Embedded internal voltage reference Figure 20. VREFINT versus temperature 6.3.5 Supply current characteristics Table 25. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) Table 26. Current consumption in Run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) Table 27. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART disable Table 28. Current consumption in Run modes, code with data processing running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Table 29. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1 Table 30. Current consumption in Run, code with data processing running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Table 31. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) Table 32. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.10 V) Table 33. Typical current consumption in Run, with different codes running from Flash, ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS (VDD12 = 1.00 V) Table 34. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART disable Table 35. Typical current consumption in Run modes, with different codes running from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) Table 36. Typical current consumption in Run modes, with different codesrunning from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V) Table 37. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1 Table 38. Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) Table 39. Typical current consumption in Run, with different codes running from SRAM1 and power supplied by external SMPS (VDD12 = 1.00 V) Table 40. Current consumption in Sleep and Low-power sleep modes, Flash ON Table 41. Current consumption in Sleep, Flash ON and power supplied by external SMPS (VDD12 = 1.10 V) Table 42. Current consumption in Low-power sleep modes, Flash in power-down Table 43. Current consumption in Stop 2 mode Table 44. Current consumption in Stop 1 mode Table 45. Current consumption in Stop 0 Table 46. Current consumption in Standby mode Table 47. Current consumption in Shutdown mode Table 48. Current consumption in VBAT mode Table 49. Peripheral current consumption 6.3.6 Wakeup time from low-power modes and voltage scaling transition times Table 50. Low-power mode wakeup timings Table 51. Regulator modes transition times Table 52. Wakeup time using USART/LPUART 6.3.7 External clock source characteristics Table 53. High-speed external user clock characteristics Figure 21. High-speed external clock source AC timing diagram Table 54. Low-speed external user clock characteristics Figure 22. Low-speed external clock source AC timing diagram Table 55. HSE oscillator characteristics Figure 23. Typical application with an 8 MHz crystal Table 56. LSE oscillator characteristics (fLSE = 32.768 kHz) Figure 24. Typical application with a 32.768 kHz crystal 6.3.8 Internal clock source characteristics Table 57. HSI16 oscillator characteristics Figure 25. HSI16 frequency versus temperature Table 58. MSI oscillator characteristics Figure 26. Typical current consumption versus MSI frequency Table 59. HSI48 oscillator characteristics Figure 27. HSI48 frequency versus temperature Table 60. LSI oscillator characteristics 6.3.9 PLL characteristics Table 61. PLL characteristics 6.3.10 Flash memory characteristics Table 62. Flash memory characteristics Table 63. Flash memory endurance and data retention 6.3.11 EMC characteristics Table 64. EMS characteristics Table 65. EMI characteristics 6.3.12 Electrical sensitivity characteristics Table 66. ESD absolute maximum ratings Table 67. Electrical sensitivities 6.3.13 I/O current injection characteristics Table 68. I/O current injection susceptibility 6.3.14 I/O port characteristics Table 69. I/O static characteristics Figure 28. I/O input characteristics Table 70. Output voltage characteristics Table 71. I/O AC characteristics Figure 29. I/O AC characteristics definition(1) 6.3.15 NRST pin characteristics Table 72. NRST pin characteristics Figure 30. Recommended NRST pin protection 6.3.16 Extended interrupt and event controller input (EXTI) characteristics Table 73. EXTI Input Characteristics 6.3.17 Analog switches booster Table 74. Analog switches booster characteristics 6.3.18 Analog-to-Digital converter characteristics Table 75. ADC characteristics Table 76. Maximum ADC RAIN Table 77. ADC accuracy - limited test conditions 1 Table 78. ADC accuracy - limited test conditions 2 Table 79. ADC accuracy - limited test conditions 3 Table 80. ADC accuracy - limited test conditions 4 Figure 31. ADC accuracy characteristics Figure 32. Typical connection diagram using the ADC 6.3.19 Comparator characteristics Table 81. COMP characteristics 6.3.20 Operational amplifiers characteristics Table 82. OPAMP characteristics 6.3.21 Temperature sensor characteristics Table 83. TS characteristics 6.3.22 VBAT monitoring characteristics Table 84. VBAT monitoring characteristics Table 85. VBAT charging characteristics 6.3.23 Timer characteristics Table 86. TIMx characteristics Table 87. IWDG min/max timeout period at 32 kHz (LSI) Table 88. WWDG min/max timeout value at 80 MHz (PCLK) 6.3.24 Communication interfaces characteristics Table 89. I2C analog filter characteristics Table 90. SPI characteristics Figure 33. SPI timing diagram - slave mode and CPHA = 0 Figure 34. SPI timing diagram - slave mode and CPHA = 1 Figure 35. SPI timing diagram - master mode Table 91. Quad SPI characteristics in SDR mode Table 92. QUADSPI characteristics in DDR mode Figure 36. Quad SPI timing diagram - SDR mode Figure 37. Quad SPI timing diagram - DDR mode Table 93. USB electrical characteristics 7 Package information 7.1 LQFP64 package information Figure 38. LQFP64 - Outline Table 94. LQFP64 - Mechanical data Figure 39. LQFP64 - Recommended footprint Figure 40. LQFP64 marking (package top view) Figure 41. LQFP64 (external SMPS device) marking (package top view) 7.2 UFBGA64 package information Figure 42. UFBGA64 - Outline Table 95. UFBGA64 - Mechanical data Figure 43. UFBGA64 - Recommended footprint Table 96. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA) Figure 44. UFBGA64 marking (package top view) Figure 45. UFBGA64 marking (package top view) 7.3 LQFP48 package information Figure 46. LQFP48 - Outline Table 97. LQFP48 - Mechanical data Figure 47. LQFP48 - Recommended footprint Figure 48. LQFP48 marking (package top view) 7.4 UFQFPN48 package information Figure 49. UFQFPN48 - Outline Table 98. UFQFPN48 - Mechanical data Figure 50. UFQFPN48 - Recommended footprint Figure 51. UFQFPN48 marking (package top view) 7.5 WLCSP36 package information Figure 52. WLCSP36 - Outline Table 99. WLCSP36 - Mechanical data Figure 53. WLCSP36 - Recommended footprint Table 100. WLCSP36 - Recommended PCB design rules Figure 54. WLCSP36 marking (package top view) 7.6 UFQFPN32 package information Figure 55. UFQFPN32 - Outline Table 101. UFQFPN32 - Mechanical data Figure 56. UFQFPN32 - Recommended footprint Figure 57. UFQFPN32 marking (package top view) 7.7 LQFP32 package information Figure 58. LQFP32 - Outline Table 102. LQFP32 - Mechanical data Figure 59. LQFP32 - Recommended footprint Figure 60. LQFP32 marking (package top view) 7.8 Thermal characteristics Table 103. Package thermal characteristics 7.8.1 Reference document 7.8.2 Selecting the product temperature range 8 Ordering information Table 104. STM32L412xx ordering information scheme 9 Revision history Table 105. Document revision history