Preliminary Datasheet EPC23101 (Efficient Power Conversion) - 5
Fabricante | Efficient Power Conversion |
Descripción | ePower Chipset 100 V, 65 A |
Páginas / Página | 9 / 5 — eGaN® FET DATASHEET. Electrical Characteristics. SYMBOL. PARAMETER. TEST … |
Formato / tamaño de archivo | PDF / 983 Kb |
Idioma del documento | Inglés |
eGaN® FET DATASHEET. Electrical Characteristics. SYMBOL. PARAMETER. TEST CONDITIONS. MIN. TYP. MAX. UNITS. Low Side Power Supply
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eGaN® FET DATASHEET
EPC23101
Electrical Characteristics
Nominal VIN = 48 V, VDRV = VDD = 5 V and (VBOOT – VSW) = 5 V. CL = 4000 pF. All typical ratings are specified at TA = 25˚C unless otherwise indicated. All voltage parameters are absolute voltages referenced to GND unless indicated otherwise.
Electrical Characteristics SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Low Side Power Supply
IDRVQ Off State Total Quiescent Current HSIN/LSIN/EN = 0 V, VDRV = VDD = 5 V 10 IDRV mA 100kHz Total Operating Current @100 kHz PWM = 100 kHz, 50% On-Time 18 IDRV1MHz Total Operating Current @1 MHz PWM = 1 MHz, 50% On-Time 37 IINdisable VIN Quiescent Current at Disable Mode EN = VDRV = 5 V, VIN = 48 V 600 µA IDRVdisable VDRV Quiescent Current at Disable Mode EN = VDRV = 5 V, VIN = 48 V 50
Bootstrap Power Supply
IBOOTQ Off State Bootstrap Supply Current HSIN = 0 V, (VBOOT – VSW) = 5 V 6 IBOOT mA 100kHz Bootstrap Supply Current @100 kHz HS PWM = 100 kHz, 50% On-Time 8 IBOOT1MHz Bootstrap Supply Current @1 MHz HS PWM = 1 MHz, 50% On-Time 20 VSYNC_BOOT Sync Boot Generated (VBOOT -VSW) ISYNC_BOOT = 20 mA 4.75 V
Undervoltage Lockout
VDDUVLO+ UVLO Trip Level VDD Rising LSIN = 5 V, VDD Ramps Up 4.0 VDDHYST UVLO VDD Falling Hysteresis LSIN = 5 V, VDD Ramps Down 0.5 V VBOOTUVLO+ UVLO Trip Level (VBOOT - VSW) Rising HSIN = 5 V, VBOOT Ramps Up 4.0 VBOOTHYST UVLO (VBOOT - VSW) Falling Hysteresis HSIN = 5 V, VBOOT Ramps Down 0.5
Logic Input Pins
VIH High-level Logic Threshold HSIN, LSIN Rising 2.4 V V IL Low-level Logic Threshold HSIN, LSIN Falling 0.8 VIHYST Logic Threshold Hysteresis VIH Rising – VIL Falling 0.3 RIN HSIN and LSIN Pull-Down Resistance HSIN, LSIN = 5 V 6.5 kΩ
VDD Disable Input
VTH_EN EN Input Threshold VDRV = 5 V 3.3 V REN EN Pul -Down Resistance EN = 5 V 150 kΩ
Low Side Gate Drive Output
RDS(on)_PU Gate Output Pull-Up FET RDS(on) RDRV = VDRV 0.4 Ω RDS(on)_PD Gate Output Pull-Down FET RDS(on) 0.4 IPU Short Circuit Pull-Up Current RDRV = VDRV, LGOUT = 0 V 5 A IPD Short Circuit Pull-Down Current LGOUT = VDRV 5
High Side Internal Power FET
RDS(on)_HS High Side FET RDS(on) IDS = +/-10 A, HSIN = 5 V, LSIN = 0 V 2.6 3.3 mΩ VHS_DS_Clamp High Side 3rd Quadrant Clamp IDS = - 10 A, HSIN & LSIN = 0 V -1.5 V ILEAK_VIN-SW Leakage Current (VIN to SW) HSIN = 0 V, VIN = 100 V, SW = 0 V 100 µA CSW Output Capacitance (SW to GND) HSIN = 0 V, VIN = 48 V, SW = 48 V 82 pF COSS_HSFET Output Capacitance (VIN to SW) HSIN = 0 V, VIN = 48 V, SW = 0 V 630 QOSS_HSFET Output Charge (VIN to SW) HSIN = 0 V, VIN = 48 V, SW = 0 V 50 nC EQOSS Output Capacitance Stored Energy HSIN = 0 V, VIN = 48 V, SW = 0 V 0.9 EON_HS_0 HS Turn-On, SW = 0 V to 48 V, R Turn-On Switching Energy (HS_FET) BOOT = 0 Ω, ILOAD = 10 A 5 µJ EON_HS_1 HS Turn-On, SW = 0 V to 48 V, RBOOT = 2.2 Ω, ILOAD = 10 A 9 EOFF_HS Turn-Off Switching Energy (HS_FET) HS Turn-Off, SW = 48 V to 0 V, ILOAD = 10 A 0.3 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 5