Datasheet RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 (Renesas) - 9
| Fabricante | Renesas |
| Descripción | Large 3V Output Swing, 5kV EFT, 16.5kV ESD, RS-485 Transceivers |
| Páginas / Página | 34 / 9 — RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 … |
| Formato / tamaño de archivo | PDF / 613 Kb |
| Idioma del documento | Inglés |
RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet. Temp. Parameter. Symbol. Test Conditions. (°C). Min[2]
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RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet
Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1].
Temp Parameter Symbol Test Conditions (°C) Min[2] Typ Max[2] Unit
Driver Enable to Output Low tZL RL = 500Ω, CL = 100pF, Full - 28 45 ns SW = V [7] CC (Figure 6) Driver Disable from Output tLZ RL = 500Ω, CL = 15pF, SW = VCC Full - 50 65 ns Low (Figure 6) Driver Disable from Output tHZ RL = 500Ω, CL = 15pF, Full - 38 60 ns High SW = GND (Figure 6) Time to Shutdown[8] tSHDN Full 60 160 600 ns Driver Enable from tZH(SHDN) RL = 500Ω, CL = 100pF, Full - - 200 ns Shutdown to Output High SW = GND[8][9] (Figure 6) Driver Enable from tZL(SHDN) RL = 500Ω, CL = 100pF, Full - - 200 ns Shutdown to Output Low SW = V [8][9] CC (Figure 6)
Receiver Switching Characteristics (115kbps and 1Mbps Versions; RAA788150 through RAA788155)
Maximum Data Rate[6] fMAX (Figure 8) Full 1 12 - Mbps Receiver Input to Output tPLH, tPHL (Figure 8) Full - 100 150 ns Delay Receiver Skew | tPLH - tPHL | tSKD (Figure 8) Full - 4 10 ns Receiver Enable to Output tZL RL = 1kΩ, CL = 15pF, Full - 9 20 ns Low SW = V [10] CC (Figure 9) Receiver Enable to Output tZH RL = 1kΩ, CL = 15pF, Full - 7 20 ns High SW = GND[10] (Figure 9) Receiver Disable from tLZ RL = 1kΩ, CL = 15pF, SW = VCC Full - 8 15 ns Output Low (Figure 9) Receiver Disable from tHZ RL = 1kΩ, CL = 15pF, SW = GND Full - 8 15 ns Output High (Figure 9) Time to Shutdown[8] tSHDN Full 60 160 600 ns Receiver Enable from tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND Full - - 200 ns Shutdown to Output High (Figure 9)[8][11] Receiver Enable from tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC Full - - 200 ns Shutdown to Output Low (Figure 9)[8][11]
Receiver Switching Characteristics (20Mbps Versions; RAA788156, RAA788158)
Maximum Data Rate[6] fMAX (Figure 8) Full 20 30 - Mbps Receiver Input to Output tPLH, tPHL (Figure 8) Full - 33 45 ns Delay Receiver Skew | tPLH - tPHL | tSKD (Figure 8) Full - 2.5 5 ns Receiver Enable to Output tZL RL = 1kΩ, CL = 15pF, Full - 8 15 ns Low SW = V [10] CC (Figure 9) Receiver Enable to Output tZH RL = 1kΩ, CL = 15pF, Full - 7 15 ns High SW = GND[10] (Figure 9) Receiver Disable from tLZ RL = 1kΩ, CL = 15pF, SW = VCC Full - 8 15 ns Output Low (Figure 9) Receiver Disable from tHZ RL = 1kΩ, CL = 15pF, SW = GND Full - 8 15 ns Output High (Figure 9) R15DS0005EU0102 Rev.1.02 Page 9 Aug 19, 2021 Document Outline Features Applications Contents 1. Overview 1.1 Typical Operating Circuit 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Recommended Operating Conditions 3.3 Thermal Information 3.4 Electrical Specifications 4. Test Circuits and Waveforms 5. Typical Performance Curves 6. Device Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Operating Modes 6.3.1 Driver Operation 6.3.2 Receiver Operation 6.4 Device Features 6.4.1 Large Output Signal Swing 6.4.2 Driver Overload Protection 6.4.3 Full-Failsafe Receiver 6.4.4 Low Current Shutdown Mode 6.4.5 Hot Plug Function 6.4.6 High EFT Immunity 6.4.7 High ESD Protection 7. Application Information 7.1 Network Design 7.1.1 Cable Type 7.1.2 Cable Length vs Data Rate 7.1.3 Topologies and Stub Lengths 7.1.4 Minimum Distance between Nodes 7.1.5 Failsafe Biasing Termination 7.2 Transient Protection 7.3 Layout Guidelines 7.3.1 Layout Example 8. Package Outline Drawings 9. Ordering Information 10. Revision History
RAA788150, RAA788152, RAA788153, RAA788155, RAA788156, RAA788158 Datasheet
Test Conditions: VCC = 4.5V to 5.5V; unless otherwise specified. Typical values are at VCC = 5V, TA = +25°C[1].
Temp Parameter Symbol Test Conditions (°C) Min[2] Typ Max[2] Unit
Driver Enable to Output Low tZL RL = 500Ω, CL = 100pF, Full - 28 45 ns SW = V [7] CC (Figure 6) Driver Disable from Output tLZ RL = 500Ω, CL = 15pF, SW = VCC Full - 50 65 ns Low (Figure 6) Driver Disable from Output tHZ RL = 500Ω, CL = 15pF, Full - 38 60 ns High SW = GND (Figure 6) Time to Shutdown[8] tSHDN Full 60 160 600 ns Driver Enable from tZH(SHDN) RL = 500Ω, CL = 100pF, Full - - 200 ns Shutdown to Output High SW = GND[8][9] (Figure 6) Driver Enable from tZL(SHDN) RL = 500Ω, CL = 100pF, Full - - 200 ns Shutdown to Output Low SW = V [8][9] CC (Figure 6)
Receiver Switching Characteristics (115kbps and 1Mbps Versions; RAA788150 through RAA788155)
Maximum Data Rate[6] fMAX (Figure 8) Full 1 12 - Mbps Receiver Input to Output tPLH, tPHL (Figure 8) Full - 100 150 ns Delay Receiver Skew | tPLH - tPHL | tSKD (Figure 8) Full - 4 10 ns Receiver Enable to Output tZL RL = 1kΩ, CL = 15pF, Full - 9 20 ns Low SW = V [10] CC (Figure 9) Receiver Enable to Output tZH RL = 1kΩ, CL = 15pF, Full - 7 20 ns High SW = GND[10] (Figure 9) Receiver Disable from tLZ RL = 1kΩ, CL = 15pF, SW = VCC Full - 8 15 ns Output Low (Figure 9) Receiver Disable from tHZ RL = 1kΩ, CL = 15pF, SW = GND Full - 8 15 ns Output High (Figure 9) Time to Shutdown[8] tSHDN Full 60 160 600 ns Receiver Enable from tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND Full - - 200 ns Shutdown to Output High (Figure 9)[8][11] Receiver Enable from tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC Full - - 200 ns Shutdown to Output Low (Figure 9)[8][11]
Receiver Switching Characteristics (20Mbps Versions; RAA788156, RAA788158)
Maximum Data Rate[6] fMAX (Figure 8) Full 20 30 - Mbps Receiver Input to Output tPLH, tPHL (Figure 8) Full - 33 45 ns Delay Receiver Skew | tPLH - tPHL | tSKD (Figure 8) Full - 2.5 5 ns Receiver Enable to Output tZL RL = 1kΩ, CL = 15pF, Full - 8 15 ns Low SW = V [10] CC (Figure 9) Receiver Enable to Output tZH RL = 1kΩ, CL = 15pF, Full - 7 15 ns High SW = GND[10] (Figure 9) Receiver Disable from tLZ RL = 1kΩ, CL = 15pF, SW = VCC Full - 8 15 ns Output Low (Figure 9) Receiver Disable from tHZ RL = 1kΩ, CL = 15pF, SW = GND Full - 8 15 ns Output High (Figure 9) R15DS0005EU0102 Rev.1.02 Page 9 Aug 19, 2021 Document Outline Features Applications Contents 1. Overview 1.1 Typical Operating Circuit 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Recommended Operating Conditions 3.3 Thermal Information 3.4 Electrical Specifications 4. Test Circuits and Waveforms 5. Typical Performance Curves 6. Device Description 6.1 Overview 6.2 Functional Block Diagram 6.3 Operating Modes 6.3.1 Driver Operation 6.3.2 Receiver Operation 6.4 Device Features 6.4.1 Large Output Signal Swing 6.4.2 Driver Overload Protection 6.4.3 Full-Failsafe Receiver 6.4.4 Low Current Shutdown Mode 6.4.5 Hot Plug Function 6.4.6 High EFT Immunity 6.4.7 High ESD Protection 7. Application Information 7.1 Network Design 7.1.1 Cable Type 7.1.2 Cable Length vs Data Rate 7.1.3 Topologies and Stub Lengths 7.1.4 Minimum Distance between Nodes 7.1.5 Failsafe Biasing Termination 7.2 Transient Protection 7.3 Layout Guidelines 7.3.1 Layout Example 8. Package Outline Drawings 9. Ordering Information 10. Revision History