Datasheet RAA227063 (Renesas) - 10

RAA227063 Datasheet Pin # Pin Name Description
7 EN IC normal operation mode enable pin. Pulling high puts the IC into normal operating mode; pulling low or being left floating puts the IC into low power Sleep mode. 8 nFAULT Fault indicator pin. This is an open-drain output pin that requires an external pull-up resistor. If not being set to take no action through the SPI interface, this pin is pulled low if any fault occurs, and released if all fault conditions are removed and all necessary power rails are up.
Note:
This pin is only in valid state 5µs after EN goes high. In shutdown mode, the internal pull-down device is disabled to lower the shutdown current. 9 IDRV/SDI Dual function pin. ▪ If the device is Eight as a hardware interface, this pin serves as the driver peak source current setting pin. Eight levels of source current settings are supported through resistor on this pin. The setting is detected and latched up after the device is put into operating mode and all the power rail soft-starts are done. ▪ If the device is configured as an SPI interface, this pin serves as the SPI data input pin. 10 MODE/SDO Dual function pin. ▪ If the device is configured as a hardware interface, this pin serves as the mode setting pin that sets PWM mode and current sensing mode. • If tied to VCC directly, the device works in 3-phase PWM mode, using ground-side shunt resistor for current sensing. • If tied to SGND through a 60.4kΩ resistor, the device works in 3-phase PWM mode and uses low-side rDS(ON) for current sensing. • If tied to SGND through a 25kΩ resistor, the device works in 3-phase HI/LI mode and uses low-side rDS(ON) for current sensing. • If tied to SGND directly, the device works in 3-phase HI/LI mode and uses ground-side shunt resistors for current sensing. The setting is detected and latched after the device is put into operating mode and all the power rail soft-starts are done. ▪ If the device is configured as an SPI interface, this pin serves as the SPI data output pin. 11 CSGAIN/SCLK Dual function pin. ▪ If the device is configured as a hardware interface, this pin serves as the shunt amplifier sensing gain setting pin. Four levels of gain (5V/V, 10V/V, 20V/V, 40V/V) settings are supported through resistors on this pin. The setting is detected and latched up after the device is put into operating mode and all the power rail soft-starts are done. ▪ If the device is configured as an SPI interface, this pin serves as the SPI clock input pin. 12 VDSTH/nSCS Dual function pin. ▪ If the device is configured as a hardware interface, this pin serves as the VDS OCP threshold setting pin. Eight levels of settings are supported through resistor on this pin. The setting is detected and latched after the device is put into operating mode and all the power rail soft-starts are done. ▪ If the device is configured as an SPI interface, this pin serves as the SPI chip select pin. R16DS0045EU0101 Rev.1.01 Page 10 Nov 29, 2021 Document Outline Applications Features Contents 1. Overview 1.1 Typical Application Circuits 2. Pin Information 2.1 Pin Assignments 2.2 Pin Descriptions 3. Specifications 3.1 Absolute Maximum Ratings 3.2 Thermal Information 3.3 Recommended Operating Conditions 3.4 Electrical Specifications 4. Typical Performance Curves 5. Functional Description 5.1 Modes of Operation and Power-On Sequence 5.1.1 Definitions of State of Different Modes 5.1.2 Mode Transition 5.1.3 Modes of Operation 5.1.3.1 Gate Driver Control Modes 5.1.3.2 3-phase HI/LI Mode 5.1.3.3 3-phase PWM Mode 5.1.4 Gate Driver Structure and Feature 5.1.4.1 Driver Structure 5.1.4.2 Adjustable Slew-Rate 5.1.4.3 Driver Robustness Enhancement 5.1.4.4 Gate Drive Diagram 5.1.4.5 Gate Drive Scheme in 3-phase HI/LI Mode 5.1.5 Power Architecture 5.1.5.1 Power Architecture Overview 5.1.5.2 Low-Side Driver Supply (VDRV) 5.1.5.3 Charge Pump 5.1.5.4 VCC Supply 5.1.5.5 MCU AUXVCC Supply 5.1.6 Power-On Sequence 5.2 Fault Management 5.2.1 Fault Conditions Types 5.2.2 nFAULT Indicator 5.3 Current Sensing and BEMF Sensing 5.3.1 Overview 5.3.2 Details on Different Sensing Configurations 5.3.2.1 Configuration 1 5.3.2.2 Configuration 2 5.3.2.3 Configuration 3 5.3.2.4 Configuration 4 5.3.2.5 Configuration 5 5.3.2.6 Configuration 6 5.3.2.7 Configuration 7 5.3.2.8 Configuration 8 5.3.2.9 Configuration 9 5.3.3 Structure of Amplifiers CSA, CSB, and CSC 5.3.4 BEMF Sensing Control Signal Logic 5.3.5 Multiplexer Control Signal Logic 5.3.6 Sample and Hold Timing Logic 5.3.7 Low-Side rDS(ON) Current Sensing Timing Logic 5.4 Hardware Interface for Parameter Setting 5.4.1 Parameter Setting Tables 5.5 Serial Peripheral Interface (SPI) 5.5.1 Communication Protocol 5.5.2 Timing Diagram 6. Register Map 7. Package Outline Drawing 8. Ordering Information 9. Revision History