Datasheet IRF540 (Vishay) - 6
| Fabricante | Vishay |
| Descripción | Power MOSFET |
| Páginas / Página | 8 / 6 — IRF540. Fig. 13a - Basic Gate Charge Waveform. Fig. 13b - Gate Charge … |
| Formato / tamaño de archivo | PDF / 155 Kb |
| Idioma del documento | Inglés |
IRF540. Fig. 13a - Basic Gate Charge Waveform. Fig. 13b - Gate Charge Test Circuit. Peak Diode Recovery dv/dt Test Circuit
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IRF540
www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. Q 50 kΩ G 10 V 12 V 0.2 µF 0.3 µF Q Q GS GD + V D.U.T. DS - VG VGS 3 mA Charge I I G D Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit Peak Diode Recovery dv/dt Test Circuit
+ Circuit layout considerations D.U.T. • Low stray inductance 3 • Ground plane • Low leakage inductance current transformer - + 2 - 4 + - 1 Rg • dv/dt controlled by R + g • Driver same type as D.U.T. V - DD • ISD controlled by duty factor “D” • D.U.T. - device under test 1 Driver gate drive P.W. Period D = P.W. Period VGS = 10 V a D.U.T. ISD waveform 2 Reverse recovery Body diode forward current current di/dt 3 D.U.T. V waveform DS Diode recovery dv/dt VDD Re-applied voltage Body diode forward drop Inductor current 4 Ripple ≤ 5 % ISD
Note
a. V = 5 V for logic level devices GS
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91021. S21-0819-Rev. C, 02-Aug-2021
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Document Number: 91021 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. Q 50 kΩ G 10 V 12 V 0.2 µF 0.3 µF Q Q GS GD + V D.U.T. DS - VG VGS 3 mA Charge I I G D Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit Peak Diode Recovery dv/dt Test Circuit
+ Circuit layout considerations D.U.T. • Low stray inductance 3 • Ground plane • Low leakage inductance current transformer - + 2 - 4 + - 1 Rg • dv/dt controlled by R + g • Driver same type as D.U.T. V - DD • ISD controlled by duty factor “D” • D.U.T. - device under test 1 Driver gate drive P.W. Period D = P.W. Period VGS = 10 V a D.U.T. ISD waveform 2 Reverse recovery Body diode forward current current di/dt 3 D.U.T. V waveform DS Diode recovery dv/dt VDD Re-applied voltage Body diode forward drop Inductor current 4 Ripple ≤ 5 % ISD
Note
a. V = 5 V for logic level devices GS
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91021. S21-0819-Rev. C, 02-Aug-2021
6
Document Number: 91021 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000