link to page 5 link to page 5 link to page 5 MC10EL16, MC100EL16Table 8. AC CHARACTERISTICS ( VCC = 5.0 V; VEE = 0 V or VCC = 0 V; V EE= −5.0 V (Note 1)) −40 ° C25 ° C85 ° CSymbolCharacteristicMinTypMaxMinTypMaxMinTypMaxUnit fmax Maximum Toggle Frequency 1.75 GHz tPLH Propagation Delay to Output ps tPHL (Diff) 125 250 375 175 250 325 205 280 355 (SE) 75 250 425 125 250 375 155 280 405 tSKEW Duty Cycle Skew (Diff) (Note 2) 5 20 5 20 5 20 ps tJITTER Random Clock Jitter (RMS) 0.7 ps VPP Input Swing (Note 3) 150 1000 150 1000 150 1000 mV tr Output Rise/Fall Times Q (20%−80%) 100 190 350 100 190 350 100 190 350 ps tf NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 1. 10 Series: VEE can vary +0.25 V / −0.5 V. 100 Series: VEE can vary +0.8 V / −0.5 V. 2. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 3. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈ 40. Q Zo = 50 W D Driver Receiver Device Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation(See Application Note AND8020/D− Termination of ECL Logic Devices)Resource Reference of Application NotesAN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com5