Datasheet PMG1-S2 (Infineon) - 10

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PMG1-S2 Datasheet
The Overvoltage/Undervoltage (OV/UV) block monitors the The I2C peripherals are compatible with the I2C Standard-mode, VBUS_C supply for programmable overvoltage and Fast-mode, and Fast-mode Plus devices as defined in the NXP undervoltage conditions. The CSA amplifies the voltage across I2C-bus specification and user manual (UM10204). an external sense resistor, which is proportional to the current being drawn from the external DC-DC VBUS supply converter. The I2C bus I/Os are implemented with GPIO in open-drain The CSA output can either be measured with an ADC or modes. configured to detect an overcurrent condition. The VBUS_P and The I2C port on SCB 1-3 blocks of PMG1-S2 are not completely VBUS_C gate drivers control the gates of external power FETs compliant with the I2C specification in the following aspects: for the VBUS_C and VBUS_P supplies. The gate drivers can be configured to support both P and N type external power FETs. ■ The GPIO cel s for SCB 1's I2C port are not overvoltage-tolerant The gate drivers are configured by default for nFET devices. In and, therefore, cannot be hot-swapped or powered up applications using pFETs, the gate drivers must be appropriately independently of the rest of the I2C system. configured. The OV/UV and CSA blocks can generate interrupts to automatically turn off the power FETs for the programmed ■ Fast-mode Plus has an IOL specification of 20 mA at a VOL of overvoltage and overcurrent conditions. The VBUS_C discharge 0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a switch allows for discharging the VBUS_C line through an VOL maximum of 0.6 V. external resistor. The USB-PD subsystem also contains two 8-bit 125 ksps ■ Fast-mode and Fast-mode Plus specify minimum Fall times, Successive Approximation Register (SAR) ADCs for analog to which are not met with the GPIO cell; Slow strong mode can digital conversions. The voltage reference for the ADCs is help meet this spec depending on the bus load. generated from the VDDD supply. Each ADC includes an 8-bit Timer/Counter/PWM Block (TCPWM) DAC and a comparator. The DAC output forms the positive input of the comparator. The negative input of the comparator is from PMG1-S2 has four TCPWM blocks. Each implements a 16-bit a 4-input multiplexer. The four inputs of the multiplexer are a pair timer, counter, pulse-width modulator (PWM), and quadrature of global analog multiplex busses, an internal bandgap voltage decoder functionality. and an internal voltage proportional to the absolute temperature.
GPIO
Each GPIO pin can be connected to the global Analog Multiplex Busses through a switch, which allows either ADC to sample the PMG1-S2 has up to 20 GPIOs (these GPIOs can be configured pin voltage. When sensing the GPIO pin voltage with an ADC, for GPIOs, SCB, SBU, and Aux signals) and SWD pins, which the pin voltage must not exceed the VDDIO supply value. can also be used as GPIOs. The I2C pins from SCB 0 are overvoltage-tolerant.
Full-Speed USB Subsystem
The GPIO block implements the following: The FSUSB subsystem contains a full-speed USB device controller as described in the Integrated Billboard Device ■ Seven drive strength modes: section. ❐ Input only ❐ Weak pull-up with strong pull-down
Peripherals
❐ Strong pull-up with weak pull-down ❐ Open drain with strong pull-down Serial Communication Blocks (SCB) ❐ Open drain with strong pull-up PMG1-S2 has four SCBs, which can be configured to implement ❐ Strong pull-up with strong pull-down an I2C, SPI, or UART interface. The hardware I2C blocks ❐ Weak pull-up with weak pull-down implement full multi-master and slave interfaces capable of multi- master arbitration. In the SPI mode, the SCB blocks can be ■ Input threshold select (CMOS or LVTTL) configured to act as master or slave. ■ Individual control of input and output buffer enabling/disabling In the I2C mode, the SCB blocks are capable of operating at in addition to the drive strength modes speeds of up to 1 Mbps (Fast Mode Plus) and have flexible buffering options to reduce interrupt overhead and latency for the ■ Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode) CPU. These blocks also support I2C that creates a mailbox address range in the memory of PMG1-S2 and effectively reduce ■ Selectable slew rates for dV/dt related noise control to improve I2C communication to reading from and writing to an array in EMI memory. In addition, the blocks support 128-deep FIFOs for During power-on and reset, the I/O pins are forced to the disable receive and transmit which, by increasing the time given for the state so as not to crowbar any inputs and/or cause excess CPU to read data, greatly reduce the need for clock stretching turn-on current. A multiplexing network known as a high-speed caused by the CPU not having read data on time. I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Document Number: 002-31598 Rev. *B Page 9 of 33 Document Outline PMG1-S2 Datasheet Power Delivery Microcontroller Gen1 PMG1 Family General Description PMG1-S2 General Description Features Type-C and USB-PD Support 32-bit MCU Subsystem Integrated Digital Blocks Clocks and Oscillators Power System-Level ESD Protection Packages Block Diagram Contents Development Support Documentation Online Tools ModusToolbox™ IDE and the PMG1 SDK Functional Overview CPU and Memory Subsystem Crypto Block Integrated Billboard Device USB-PD Subsystem (USBPD SS) Full-Speed USB Subsystem Peripherals GPIO Power Systems Overview Pinouts Application Diagrams Electrical Specifications Absolute Maximum Ratings Device-Level Specifications Digital Peripherals System Resources Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support