Datasheet AEM10330 (E-peas) - 3
| Fabricante | E-peas |
| Descripción | Highly Versatile, Regulated Single-Output, Buck-Boost Ambient Energy Manager for Up to 7-cell Solar Panels with Optional Primary |
| Páginas / Página | 33 / 3 — DATASHEET. AEM10330. List of Figures |
| Formato / tamaño de archivo | PDF / 3.9 Mb |
| Idioma del documento | Inglés |
DATASHEET. AEM10330. List of Figures
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DATASHEET AEM10330 List of Figures
Figure 1: Simplified Schematic View . 5 Figure 2: Pinout Diagram QFN 40-pin . 6 Figure 3: Functional Block Diagram . 11 Figure 4: Simplified Schematic View of the AEM10330 . 12 Figure 5: Diagram of the AEM10330 States . 14 Figure 6: Maximum LOAD Current Depending on VSTO and on VLOAD . 16 Figure 7: Custom Mode Settings . 18 Figure 8: RZMPP Connection to the AEM10330 . 19 Figure 9: VPRIM,MIN Configuration Through a Resistive Divider . 20 Figure 10: Typical Application Circuit 1 . 22 Figure 11: Typical Application Circuit 2 . 23 Figure 12: Wake-up state, Start state and Supply state . 25 Figure 13: Supply state, Shutdown state and Reset state . 25 Figure 14: Primary State . 26 Figure 15: DCDC Efficiency from SRC to STO for 1 mA and 10 mA in Low Power Mode . 27 Figure 16: DCDC Efficiency from SRC to STO for 10 mA and 50 mA in High Power Mode . 27 Figure 17: DCDC Efficiency from STO to LOAD in Low Power Mode . 28 Figure 18: DCDC Efficiency from STO to LOAD in High Power Mode . 28 Figure 19: Quiescent Current . 29 Figure 20: Schematic Example . 30 Figure 21: Layout Example for the AEM10330 and its Passive Components . 31 Figure 22: QFN 40-pin 5x5mm Drawing (Al Dimensions in mm) . 32 Figure 23: Recommended Board Layout for QFN40 package (Al Dimensions in mm) . 33 DS_AEM10330_Rev1.0 Copyright © 2021 e-peas SA 3 Document Outline 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. DCDC Converter 7.2. Reset, Wake Up and Start States 7.2.1. Storage Element Priority Supercapacitor as a Storage Element Battery as a Storage Element 7.2.2. Load Priority 7.3. Supply State 7.4. Shutdown State 7.5. Sleep State 7.6. Primary Battery State 7.7. Maximum Power Point Tracking 7.8. Balancing for Dual-Cell Supercapacitor 8. System Configuration 8.1. High Power / Low Power Mode 8.2. Storage Element Configuration 8.3. Load Configuration 8.4. Custom Mode Configuration 8.5. Disable Storage Element Charging 8.6. MPPT Configuration 8.7. ZMPP Configuration 8.8. Source to Storage Element Feed- Through 8.9. Primary Battery Configuration 8.10. External Components 8.10.1. Storage element information 8.10.2. External inductor information 8.10.3. External capacitors information CSRC CINT CLOAD 9. Typical Application Circuits 9.1. Example Circuit 1 9.2. Example Circuit 2 9.3. Circuit Behaviour 10. Performance Data 10.1. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 10.2. DCDC Conversion Efficiency From SRC to STO in High Power Mode 10.3. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode 10.4. DCDC Conversion Efficiency From STO to LOAD in High Power Mode 10.5. Quiescent Current 11. Schematic 12. Layout 13. Package Information 13.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) 13.2. Board Layout 14. Revision History
DATASHEET AEM10330 List of Figures
Figure 1: Simplified Schematic View . 5 Figure 2: Pinout Diagram QFN 40-pin . 6 Figure 3: Functional Block Diagram . 11 Figure 4: Simplified Schematic View of the AEM10330 . 12 Figure 5: Diagram of the AEM10330 States . 14 Figure 6: Maximum LOAD Current Depending on VSTO and on VLOAD . 16 Figure 7: Custom Mode Settings . 18 Figure 8: RZMPP Connection to the AEM10330 . 19 Figure 9: VPRIM,MIN Configuration Through a Resistive Divider . 20 Figure 10: Typical Application Circuit 1 . 22 Figure 11: Typical Application Circuit 2 . 23 Figure 12: Wake-up state, Start state and Supply state . 25 Figure 13: Supply state, Shutdown state and Reset state . 25 Figure 14: Primary State . 26 Figure 15: DCDC Efficiency from SRC to STO for 1 mA and 10 mA in Low Power Mode . 27 Figure 16: DCDC Efficiency from SRC to STO for 10 mA and 50 mA in High Power Mode . 27 Figure 17: DCDC Efficiency from STO to LOAD in Low Power Mode . 28 Figure 18: DCDC Efficiency from STO to LOAD in High Power Mode . 28 Figure 19: Quiescent Current . 29 Figure 20: Schematic Example . 30 Figure 21: Layout Example for the AEM10330 and its Passive Components . 31 Figure 22: QFN 40-pin 5x5mm Drawing (Al Dimensions in mm) . 32 Figure 23: Recommended Board Layout for QFN40 package (Al Dimensions in mm) . 33 DS_AEM10330_Rev1.0 Copyright © 2021 e-peas SA 3 Document Outline 1. Introduction 2. Absolute Maximum Ratings 3. Thermal Resistance 4. Typical Electrical Characteristics at 25 °C 5. Recommended Operation Conditions 6. Functional Block Diagram 7. Theory of Operation 7.1. DCDC Converter 7.2. Reset, Wake Up and Start States 7.2.1. Storage Element Priority Supercapacitor as a Storage Element Battery as a Storage Element 7.2.2. Load Priority 7.3. Supply State 7.4. Shutdown State 7.5. Sleep State 7.6. Primary Battery State 7.7. Maximum Power Point Tracking 7.8. Balancing for Dual-Cell Supercapacitor 8. System Configuration 8.1. High Power / Low Power Mode 8.2. Storage Element Configuration 8.3. Load Configuration 8.4. Custom Mode Configuration 8.5. Disable Storage Element Charging 8.6. MPPT Configuration 8.7. ZMPP Configuration 8.8. Source to Storage Element Feed- Through 8.9. Primary Battery Configuration 8.10. External Components 8.10.1. Storage element information 8.10.2. External inductor information 8.10.3. External capacitors information CSRC CINT CLOAD 9. Typical Application Circuits 9.1. Example Circuit 1 9.2. Example Circuit 2 9.3. Circuit Behaviour 10. Performance Data 10.1. DCDC Conversion Efficiency From SRC to STO in Low Power Mode 10.2. DCDC Conversion Efficiency From SRC to STO in High Power Mode 10.3. DCDC Conversion Efficiency From STO to LOAD in Low Power Mode 10.4. DCDC Conversion Efficiency From STO to LOAD in High Power Mode 10.5. Quiescent Current 11. Schematic 12. Layout 13. Package Information 13.1. Plastic Quad Flatpack No-Lead (QFN 40-pin 5x5mm) 13.2. Board Layout 14. Revision History